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DG540DN-T1-E3 PDF预览

DG540DN-T1-E3

更新时间: 2024-11-10 14:49:03
品牌 Logo 应用领域
威世 - VISHAY 输出元件
页数 文件大小 规格书
11页 109K
描述
IC QUAD 1-CHANNEL, AUDIO/VIDEO SWITCH, PQCC20, PLASTIC, LCC-20, Multiplexer or Switch

DG540DN-T1-E3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QLCC
包装说明:QCCJ, LDCC20,.4SQ针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26其他特性:VIDEO APPLICATION
模拟集成电路 - 其他类型:AUDIO/VIDEO SWITCHJESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.965 mm
湿度敏感等级:1标称负供电电压 (Vsup):-3 V
正常位置:NO信道数量:1
功能数量:4端子数量:20
标称断态隔离度:80 dB通态电阻匹配规范:2 Ω
最大通态电阻 (Ron):60 Ω最高工作温度:85 °C
最低工作温度:-40 °C输出:SEPARATE OUTPUT
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
电源:15,-3 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Multiplexer or Switches
标称供电电压 (Vsup):15 V表面贴装:YES
最长断开时间:50 ns最长接通时间:70 ns
切换:BREAK-BEFORE-MAKE技术:NMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:8.965 mmBase Number Matches:1

DG540DN-T1-E3 数据手册

 浏览型号DG540DN-T1-E3的Datasheet PDF文件第2页浏览型号DG540DN-T1-E3的Datasheet PDF文件第3页浏览型号DG540DN-T1-E3的Datasheet PDF文件第4页浏览型号DG540DN-T1-E3的Datasheet PDF文件第5页浏览型号DG540DN-T1-E3的Datasheet PDF文件第6页浏览型号DG540DN-T1-E3的Datasheet PDF文件第7页 
DG540/541/542  
Vishay Siliconix  
Wideband/Video “T” Switches  
FEATURES  
BENEFITS  
APPLICATIONS  
D Wide Bandwidth: 500 MHz  
D Low Crosstalk: –85 dB  
D Flat Frequency Response  
D High Color Fidelity  
D RF and Video Switching  
D RGB Switching  
D High Off-Isolation: –80 dB @ 5 MHz  
D “T” Switch Configuration  
D Low Insertion Loss  
D Local and Wide Area Networks  
D Video Routing  
D Improved System Performance  
D Reduced Board Space  
D Reduced Power Consumption  
D Improved Data Throughput  
D TTL and CMOS Logic Compatible  
D Fast Switching—tON: 45 ns  
D Low rDS(on): 30 W  
D Fast Data Acquisition  
D ATE  
D Radar/FLR Systems  
D Video Multiplexing  
DESCRIPTION  
The DG540/541/542 are high performance monolithic  
wideband/video switches designed for switching RF, video  
and digital signals. By utilizing a “T” switch configuration on  
each channel, these devices achieve exceptionally low  
crosstalk and high off-isolation. The crosstalk and off-isolation  
of the DG540 are further improved by the introduction of extra  
GND pins between signal pins.  
To achieve TTL compatibility, low channel capacitances and  
fast switching times, the DG540 family is built on the  
Vishay Siliconix proprietary D/CMOS process. Each switch  
conducts equally well in both directions when on.  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
DG540  
DG540  
Dual-In-Line  
PLCC  
IN  
D
IN  
D
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
1
2
3
2
1
20 19  
GND  
GND  
3
4
5
6
7
8
18  
17  
16  
S
GND  
TRUTH TABLE  
1
S
1
S
2
4
V–  
S
2
Logic  
Switch  
V–  
V+  
5
GND  
V+  
0
1
OFF  
ON  
GND  
GND  
S
4
15 GND  
14  
6
GND  
S
3
S
4
S
3
7
Logic “0” v 0.8 V  
Logic “1” w 2 V  
GND  
GND  
8
9
10 11 12 13  
Top View  
D
D
3
9
4
IN  
4
IN  
3
10  
Top View  
Document Number: 70055  
S-00399—Rev. G, 13-Sep-99  
www.vishay.com S FaxBack 408-970-5600  
4-1  

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