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DG529CY

更新时间： 2024-11-11 22:49:03
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英特矽尔 - INTERSIL 复用器
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16页 311K
描述
Analog CMOS Latchable Multiplexers

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DG529CY 数据手册

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DG526, DG527,  
DG528, DG529  
Semiconductor  
Analog CMOS  
April 1999  
Latchable Multiplexers  
Features  
Description  
• Direct RESET  
The DG526, DG527, DG528, and DG529 are CMOS  
Monolithic 16-Channel/Dual 4-Channel Analog Multiplexers.  
Each device has on-chip address and control latches to sim-  
plify design in microprocessor based applications. The DG526  
uses 4 address lines to control its 16 channels; the DG527,  
DG528 both use 3 address lines to control their 8 channels;  
and the DG529 uses 2 address lines to control its 4 channels.  
The enable pin is used to enable the address latches during  
the WR pulse. It can be hard wired to the logic supply if one of  
the channels will always be used (except during a reset) or it  
can be tied to address decoding circuitry for memory mapped  
operation. The RS pin is used to clear all latches regardless of  
the state of any other latch or control line. The WR pin is used  
to transfer the state of the address control lines to their  
latches, except during a reset or when EN is low.  
• TTL and CMOS Compatible Address and Enable  
Inputs  
• Maximum Power Supply Rating . . . . . . . . . . . . . . . .44V  
• Break-Before-Make Switching  
• Alternate Source  
Applications  
• Data Acquisition Systems  
• Communication Systems  
• Automatic Test Equipment  
• Microprocessor Controlled Systemd  
A channel in the ON state conducts signals equally well in  
both directions. In the OFF state each channel blocks volt-  
ages up to the supply rails. The address inputs, WR, RS and  
the enable input are TTL and CMOS compatible over the full  
specified operation temperature range.  
Part Number Information  
PART  
NUMBER  
TEMP.  
RANGE ( C)  
PART  
NUMBER  
TEMP.  
RANGE ( C)  
o
o
PACKAGE  
PKG. NO.  
F28.6  
F28.6  
F28.6  
M28.3  
E28.6  
F28.6  
M28.3  
F28.6  
F28.6  
F28.6  
M28.3  
E28.6  
F28.6  
M28.3  
PACKAGE  
PKG. NO.  
F18.3  
F18.3  
F18.3  
M18.3  
E18.3  
F18.3  
M18.3  
F18.3  
F18.3  
F18.3  
M18.3  
E18.3  
F18.3  
M18.3  
DG526AK  
-55 to 125 28 Ld CERDIP  
-55 to 125 28 Ld CERDIP  
DG528AK  
-55 to 125 18 Ld CERDIP  
-55 to 125 18 Ld CERDIP  
DG526AK/883B  
DG526BK  
DG526BY  
DG526CJ  
DG528AK/883B  
DG528BK  
DG528BY  
DG528CJ  
-25 to 85  
-25 to 85  
0 to 70  
28 Ld CERDIP  
28 Ld SOIC  
28 Ld PDIP  
-25 to 85  
-25 to 85  
0 to 70  
18 Ld CERDIP  
18 Ld SOIC  
18 Ld PDIP  
DG526CK  
DG526CY  
DG527AK  
DG527AK/883B  
DG527BK  
DG527BY  
DG527CJ  
0 to 70  
28 Ld CERDIP  
28 Ld SOIC  
DG528CK  
DG528CY  
DG529AK  
DG529AK/883B  
DG529BK  
DG529BY  
DG529CJ  
0 to 70  
18 Ld CERDIP  
18 Ld SOIC  
0 to 70  
0 to 70  
-55 to 125 28 Ld CERDIP  
-55 to 125 28 Ld CERDIP  
-55 to 125 18 Ld CERDIP  
-55 to 125 18 Ld CERDIP  
-25 to 85  
-25 to 85  
0 to 70  
28 Ld CERDIP  
28 Ld SOIC  
28 Ld PDIP  
-25 to 85  
-25 to 85  
0 to 70  
18 Ld CERDIP  
18 Ld SOIC  
18 Ld PDIP  
DG527CK  
DG527CY  
0 to 70  
28 Ld CERDIP  
28 Ld SOIC  
DG529CK  
DG529CY  
0 to 70  
18 Ld CERDIP  
18 Ld SOIC  
0 to 70  
0 to 70  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 3139.2  
Copyright © Harris Corporation 1999  
12-1  
1234567...16

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