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DG528DN PDF预览

DG528DN

更新时间: 2024-11-12 10:03:51
品牌 Logo 应用领域
威世 - VISHAY 复用器开关复用器或开关信号电路
页数 文件大小 规格书
12页 175K
描述
Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers

DG528DN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC20,.4SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.67
模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXERJESD-30 代码:S-PQCC-J20
JESD-609代码:e0标称负供电电压 (Vsup):-15 V
信道数量:8功能数量:1
端子数量:20最大通态电阻 (Ron):550 Ω
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:+-15 V
认证状态:Not Qualified最大信号电流:0.02 A
子类别:Multiplexer or Switches最大供电电流 (Isup):2.5 mA
标称供电电压 (Vsup):15 V表面贴装:YES
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUADBase Number Matches:1

DG528DN 数据手册

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DG528, DG529  
Vishay Siliconix  
Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers  
DESCRIPTION  
FEATURES  
Low RDS(on): 270  
The DG528 is an 8-channel single-ended analog multiplexer  
designed to connect one of eight inputs to a common output  
as determined by a 3-bit binary address (A0, A1, A2). DG529,  
a 4-channel dual analog multiplexer, is designed to connect  
one of four differential inputs to a common differential output  
as determined by its 2-bit binary address (A0, A1) logic.  
44 V Power Supply Rating  
On-Board Address Latches  
Break-Before-Make  
Low Leakage - ID(on): 30 pA  
BENEFITS  
These analog multiplexers have on-chip address and control  
latches to simplify design in microprocessor based applica-  
tions. Break-before-make switching action protects against  
momentary shorting of the input signals. The DG528/529 are  
built on the improved PLUS-40 CMOS process. A buried  
layer prevents latchup.  
Improved System Accuracy  
Microporcessor Bus Compatible  
Easily Interfaced  
Reduced Crosstalk  
APPLICATIONS  
Data Acquisition Systems  
Automatic Test Equipment  
Avionics and Military Systems  
Medical Instrumentation  
The on chip TTL-compatible address latches simplify digital  
interface design and reduce board space in data acquisition  
systems, process controls, avionics, and ATE.  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
DG529  
Dual-In-Line  
DG528  
Dual-In-Line  
DG528  
PLCC  
WR  
RS  
WR  
RS  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
0
3
2
1
20 19  
A
0
A
1
A
0
A
1
EN  
V-  
GND  
V+  
EN  
V-  
A
2
Latches  
Latches  
EN  
4
5
6
7
8
18  
17  
16  
15  
14  
A
2
Latches  
GND  
V+  
±
V
GND  
V+  
Decoders/Drivers  
Decoders/Drivers  
Decoders/Drivers  
S
1
S
2
S
3
S
1a  
S
1b  
S
1
S
5
S
2a  
S
2b  
S
2
S
5
S
6
S
3a  
S
3b  
S
3
S
6
S
4a  
S
4b  
S
4
S
7
9
10 11 12 13  
Top View  
D
a
D
b
D
S
8
1
Top View  
Top View  
Document Number: 70068  
S11-1029–Rev. D, 23-May-11  
www.vishay.com  
1
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  

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