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DG485DN-E3 PDF预览

DG485DN-E3

更新时间: 2024-11-09 14:49:03
品牌 Logo 应用领域
威世 - VISHAY 输出元件
页数 文件大小 规格书
11页 101K
描述
Multiplexers/Switches, 8 Func, CMOS, PQCC20

DG485DN-E3 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:QCCJ, LDCC20,.4SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:NJESD-30 代码:S-PQCC-J20
JESD-609代码:e3湿度敏感等级:1
正常位置:NO功能数量:8
端子数量:20最大通态电阻 (Ron):125 Ω
最高工作温度:85 °C最低工作温度:-40 °C
输出:COMMON OUTPUT封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:5,+-15 V认证状态:Not Qualified
子类别:Multiplexer or Switches表面贴装:YES
最长接通时间:200 ns切换:BREAK-BEFORE-MAKE
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

DG485DN-E3 数据手册

 浏览型号DG485DN-E3的Datasheet PDF文件第2页浏览型号DG485DN-E3的Datasheet PDF文件第3页浏览型号DG485DN-E3的Datasheet PDF文件第4页浏览型号DG485DN-E3的Datasheet PDF文件第5页浏览型号DG485DN-E3的Datasheet PDF文件第6页浏览型号DG485DN-E3的Datasheet PDF文件第7页 
DG485  
Vishay Siliconix  
Octal Analog Switch Array  
FEATURES  
BENEFITS  
APPLICATIONS  
D Low On-Resistance: 55 W  
D Rail-to-Rail Analog Input Range  
D Serial Interface  
D Low Signal Distortion  
D Audio Switching and Routing  
D Devices Can Be Chained for System D Audio Teleconferencing  
Expansion  
D Data Acquisition and Industrial  
D Reduced Board Space  
D Reduced Switch Errors  
Process Control  
D Low-Power—PD: 35 nW  
D TTL and CMOS Compatible  
D Battery Powered Remote Systems  
D Reduced Power Supply  
D Automotive, Avionics and ATE  
D Any Combination of 8 SPST to the  
Requirements  
Systems  
Output  
D Simple Interfacing  
D Summing Amplifiers  
D High Speed—tON: 170 ns  
DESCRIPTION  
The DG485 is an analog switch array consisting of eight SPST  
switches connected to a common output. This device may be  
used as an 8-channel multiplexer in serial control applications.  
Any, all or none of the eight switches may be closed at any  
serial output (DOUT) allow daisy chaining of multiple arrays for  
large systems.  
W
given time. Combining low on-resistance (rDS(on) 55 , typ.)  
Built on the Vishay Siliconix high voltage silicon gate process  
the DG485 has a wide 44-V power supply voltage rating. An  
epitaxial layer prevents latchup.  
and fast switching (tON: 170 ns, typ.), the DG485 is ideally  
suited for data acquisition, process control, communication,  
and avionic applications.  
Eachchannelconductsequallywellineitherdirectionwhenon  
and blocks up to rail-to-rail voltages when off.  
Control data is input serially into the shift register with each  
clock pulse. The shift register contents can be latched-in (via  
LD) at any point into an octal latch which in turn controls all  
switches. RS resets the shift register, forcing all latch inputs to  
a low condition (all switches off). The serial input (DIN) and  
For additional information please refer to application note  
AN204.  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
PLCC and LCC  
Dual-In-Line  
LD  
RS  
GND  
D
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
3
2
1
20 19  
V
S
S
S
S
L
4
3
S
S
S
S
4
5
6
7
8
18  
17  
16  
15  
14  
D
S
4
3
2
1
S
5
5
S
6
S
S
S
2
1
6
S
S
7
7
V+  
8
Shift Register/Latches  
10 11 12 13  
V+  
8
9
D
IN  
V–  
Shift Register  
Latches  
CLK  
D
OUT  
Top View  
Top View  
Document Number: 70065  
S-52433—Rev. E, 06-Sep-99  
www.vishay.com S FaxBack 408-970-5600  
5-1  

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