DG406/407
Vishay Siliconix
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers
DESCRIPTION
FEATURES
The DG406 is a 16-channel single-ended analog multiplexer
designed to connect one of sixteen inputs to a common
output as determined by a 4-bit binary address. The DG407
selects one of eight differential inputs to a common
differential output. Break-before-make switching action
protects against momentary shorting of inputs.
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Low On-Resistance - rDS(on): 50 Ω
Low Charge Injection - Q: 15 pC
Fast Transition Time - tTRANS: 200 ns
Low Power: 0.2 mW
Single Supply Capability
44 V Supply Max Rating
Pb-free
Available
RoHS*
COMPLIANT
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
BENEFITS
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Higher Accuracy
Reduced Glitching
Improved Data Throughput
Reduced Power Consumption
Increased Ruggedness
Applications for the DG406/407 include high speed data
acquisition, audio signal switching and routing, ATE
systems, and avionics. High performance and low power
dissipation make them ideal for battery operated and remote
instrumentation applications. For additional application
information order Faxback document numbers 70601 and
70604.
Wide Supply Ranges: 5 V to 20 V
APPLICATIONS
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Data Acquisition Systems
Audio Signal Routing
Medical Instrumentation
ATE Systems
Battery Powered Systems
High-Rel Systems
Designed in the 44 V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 volts,
allowing operation with 20 V supplies. Additionally single
(12 V) supply operation is allowed. An epitaxial layer
prevents latchup.
Single Supply Systems
For applications information please request FaxBack
documents 70601 and 70604.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG407
DG406
Dual-In-Line and SOIC Wide-Body
Dual-In-Line and SOIC Wide-Body
V+
D
a
V+
D
V-
S
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
b
V-
NC
NC
NC
S
8a
8
3
3
S
8b
S
7a
S
16
S
7
S
6
S
5
S
4
S
3
S
2
S
1
4
4
S
7b
S
6a
S
15
5
5
S
6b
S
5a
S
14
6
6
S
5b
S
4a
S
13
7
7
S
4b
S
3a
S
12
8
8
S
3b
S
2a
S
11
9
2
9
S
2b
S
1a
S
10
10
11
12
13
14
10
11
12
13
14
S
1b
EN
S
9
EN
GND
NC
A
0
GND
NC
A
0
Decoders/Drivers
Decoders/Drivers
Top View
A
1
A
1
NC
A
2
A
3
A
2
Top View
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 70061
S-71009–Rev. I, 14-May-07
www.vishay.com
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