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DG406B_11 PDF预览

DG406B_11

更新时间: 2024-11-30 10:03:39
品牌 Logo 应用领域
威世 - VISHAY 复用器
页数 文件大小 规格书
16页 202K
描述
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers

DG406B_11 数据手册

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DG406B, DG407B  
Vishay Siliconix  
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers  
DESCRIPTION  
FEATURES  
Low on-resistance - RDS(on): 45  
Low charge injection - Q: 11 pC  
Fast transition time - tTRANS: 115 ns  
Low oower: 0.2 mW  
The DG406B is  
a 16-channel single-ended analog  
multiplexer designed to connect one of sixteen inputs to a  
common output as determined by a 4-bit binary address. The  
DG407B selects one of eight differential inputs to a common  
differential output. Break-before-make switching action  
protects against momentary shorting of inputs.  
Single supply capability  
BENEFITS  
An on channel conducts current equally well in both  
directions. In the off state each channel blocks voltages up  
to the power supply rails. An enable (EN) function allows the  
user to reset the multiplexer/demultiplexer to all switches off  
for stacking several devices. All control inputs, address (Ax)  
and enable (EN) are TTL compatible over the full specified  
operating temperature range.  
Higher accuracy  
Reduced glitching  
Improved data throughput  
Reduced power consumption  
Increased ruggedness  
Wide supply ranges: 5 V to 20 V  
Applications for the DG406B, DG407B include high speed  
data acquisition, audio signal switching and routing, ATE  
systems, and avionics. High performance and low power  
dissipation make them ideal for battery operated and remote  
instrumentation applications.  
APPLICATIONS  
Data acquisition systems  
Audio signal routing  
Medical instrumentation  
ATE systems  
Designed in the 44 V silicon-gate CMOS process, the  
absolute maximum voltage rating is extended to 44 volts,  
allowing operation with 20 V supplies. Additionally single  
(12 V) supply operation is allowed. An epitaxial layer  
prevents latchup.  
Battery powered systems  
High-rel systems  
Single supply systems  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
DG406B  
DG407B  
Dual-In-Line and SOIC Wide-Body  
Dual-In-Line and SOIC Wide-Body  
V+  
NC  
NC  
D
V+  
D
a
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V-  
D
b
V-  
S
S
8
NC  
8a  
3
3
S
S
7
S
S
S
S
S
S
S
S
16  
8b  
7a  
6a  
5a  
4a  
3a  
2a  
1a  
4
4
S
S
6
S
15  
7b  
5
5
S
S
5
S
14  
6b  
6
6
S
S
4
S
13  
5b  
7
7
S
S
3
S
12  
4b  
8
8
S
S
2
S
11  
3b  
9
9
S
S
1
S
10  
2b  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
S
9
EN  
S
EN  
1b  
GND  
NC  
A
0
GND  
NC  
A
0
Decoders/Drivers  
Top View  
Decoders/Drivers  
Top View  
A
1
A
1
A
3
A
2
NC  
A
2
* Pb containing terminations are not RoHS compliant, exemptions may apply  
Document Number: 72552  
S11-0179-Rev. C, 07-Feb-11  
www.vishay.com  
1

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