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DG309CJ-E3 PDF预览

DG309CJ-E3

更新时间: 2024-11-06 06:53:03
品牌 Logo 应用领域
威世 - VISHAY 复用器开关复用器或开关信号电路光电二极管输出元件PC
页数 文件大小 规格书
6页 99K
描述
Quad Monolithic SPST CMOS Analog Switches

DG309CJ-E3 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:1.25
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:603037Samacsys Pin Count:16
Samacsys Part Category:Undefined or MiscellaneousSamacsys Package Category:Dual-In-Line Packages
Samacsys Footprint Name:PDIP 16-LEADSamacsys Released Date:2017-01-12 11:18:21
Is Samacsys:N模拟集成电路 - 其他类型:SPST
JESD-30 代码:R-PDIP-T16JESD-609代码:e3
长度:20.13 mm湿度敏感等级:1
标称负供电电压 (Vsup):-15 V正常位置:NC
信道数量:1功能数量:4
端子数量:16标称断态隔离度:78 dB
最大通态电阻 (Ron):100 Ω最高工作温度:70 °C
最低工作温度:输出:SEPARATE OUTPUT
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:+-15 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Multiplexer or Switches
标称供电电压 (Vsup):15 V表面贴装:NO
最长断开时间:150 ns最长接通时间:200 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

DG309CJ-E3 数据手册

 浏览型号DG309CJ-E3的Datasheet PDF文件第2页浏览型号DG309CJ-E3的Datasheet PDF文件第3页浏览型号DG309CJ-E3的Datasheet PDF文件第4页浏览型号DG309CJ-E3的Datasheet PDF文件第5页浏览型号DG309CJ-E3的Datasheet PDF文件第6页 
DG308A/DG309  
Vishay Siliconix  
Quad Monolithic SPST CMOS Analog Switches  
DESCRIPTION  
FEATURES  
15 V Analog Input Range  
Featuring low on-resistance (60 Ω) and fast switching  
(130 ns), the DG308A is supplied in the “normally open”  
configuration while DG309 is supplied “normally closed”.  
Input thresholds are high voltage CMOS compatible.  
Pb-free  
Low On-Resistance: 60 Ω  
Fast Switching: 130 ns  
Available  
RoHS*  
COMPLIANT  
Low Power Dissipation: 30 nW  
CMOS Logic Compatible  
Designed with the Vishay Siliconix PLUS-40 CMOS process  
to combine low power dissipation with a high breakdown  
voltage rating of 44 V, each switch conducts equally well in  
both directions when on, and blocks up to the supply voltage  
when off. An epitaxial layer prevents latch up.  
BENEFITS  
Full Rail-to-Rail Analog Signal Range  
Low Signal Error  
The DG308B/309B upgrades are recommended for new  
designs.  
Wide Dynamic Range  
Single or Dual Supply Capability  
Static Protected Logic Inputs  
Space Savings (TSSOP)  
APPLICATIONS  
Portable and Battery Powered Instrumentation  
Communication Systems  
Computer Peripherals  
High-Speed Multiplexing  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
DG308A  
IN  
D
1
1
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
IN  
D
For SPST Switches per Package  
2
TRUTH TABLE  
2
Logic  
0
1
DG308A  
OFF  
ON  
DG309  
ON  
OFF  
S
S
2
V–  
V+  
Logic "0" 3.5 V  
Logic "1" 11 V  
GND  
NC  
S
S
3
4
4
4
D
D
3
IN  
IN  
3
9
Top View  
* Pb containing terminations are not RoHS compliant, exemptions may apply  
Document Number: 70046  
S-71155–Rev. F, 11-Jun-07  
www.vishay.com  
1

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