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DG301AAA PDF预览

DG301AAA

更新时间: 2024-09-29 04:14:31
品牌 Logo 应用领域
TEMIC 复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
10页 98K
描述
CMOS Analog Switches

DG301AAA 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.56Is Samacsys:N
模拟集成电路 - 其他类型:SPDTJESD-30 代码:O-MBCY-W10
标称负供电电压 (Vsup):-15 V信道数量:1
功能数量:1端子数量:10
标称断态隔离度:62 dB最大通态电阻 (Ron):50 Ω
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:METAL封装形状:ROUND
封装形式:CYLINDRICAL认证状态:Not Qualified
最大供电电流 (Isup):1 mA标称供电电压 (Vsup):15 V
表面贴装:NO最长断开时间:250 ns
最长接通时间:300 ns技术:CMOS
温度等级:MILITARY端子形式:WIRE
端子位置:BOTTOMBase Number Matches:1

DG301AAA 数据手册

 浏览型号DG301AAA的Datasheet PDF文件第2页浏览型号DG301AAA的Datasheet PDF文件第3页浏览型号DG301AAA的Datasheet PDF文件第4页浏览型号DG301AAA的Datasheet PDF文件第5页浏览型号DG301AAA的Datasheet PDF文件第6页浏览型号DG301AAA的Datasheet PDF文件第7页 
DG300A/301A/302A/303A  
CMOS Analog Switches  
Features  
Benefits  
Applications  
D Analog Signal Range: "15 V  
D Fast Switching—tON: 150 ns  
D Low On-Resistance—rDS(on): 30 W  
D Single Supply Operation  
D Latch-up Proof  
D Full Rail-to-Rail Analog Signal  
D Low Level Switching Circuits  
Range  
D Programmable Gain Amplifiers  
D Low Signal Error  
D Portable and Battery Powered  
D Low Power Dissipation  
Systems  
D CMOS Compatible  
Description  
The DG300A-DG303A family of monolithic CMOS In the on condition the switches conduct equally well in  
switches feature three switch configuration options (SPST, both directions (with no offset voltage) and minimize error  
SPDT, and DPST) for precision applications in conditions with their low on-resistance.  
communications, instrumentation and process control,  
where low leakage switching combined with low power  
consumption are required.  
Featuring low power consumption (3.5 mW typ) these  
switches are ideal for battery powered applications, without  
Designed on the Siliconix PLUS-40 CMOS process, these sacrificing  
switching  
speed.  
Designed  
for  
switches are latch-up proof, and are designed to block up to break-before-make switching action, these devices are  
30 V peak-to-peak when off. An epitaxial layer prevents CMOS and quasi TTL compatible. Single supply operation  
latchup.  
is allowed by connecting the V– rail to 0 V.  
Functional Block Diagram and Pin Configuration  
DG300A  
Dual-In-Line  
DG300A  
Metal Can  
V+ (Substrate and Case)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
NC  
V+  
D
D
2
1
D
D
1
2
10  
NC  
NC  
1
4
9
6
Truth Table  
S
S
1
2
S
1
S
2
Logic  
Switch  
OFF  
2
3
8
0
1
NC  
NC  
7
ON  
IN  
Top View  
2
IN  
IN  
1
1
IN  
2
Logic “0” v 0.8 V  
Logic “1” w 4 V  
8
Top View  
GND  
V–  
5
NC  
V–  
GND  
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70044.  
Siliconix  
1
S-52880—Rev. C, 28-Apr-97  

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