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DG2042DQ-T1-E3 PDF预览

DG2042DQ-T1-E3

更新时间: 2024-11-27 10:03:27
品牌 Logo 应用领域
威世 - VISHAY 复用器开关复用器或开关信号电路光电二极管输出元件
页数 文件大小 规格书
14页 229K
描述
Low-Voltage, Low RON Quad SPST Analog Switch

DG2042DQ-T1-E3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.77模拟集成电路 - 其他类型:SPST
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm湿度敏感等级:1
正常位置:NO信道数量:1
功能数量:4端子数量:16
标称断态隔离度:63 dB通态电阻匹配规范:0.4 Ω
最大通态电阻 (Ron):6.3 Ω最高工作温度:85 °C
最低工作温度:-40 °C输出:SEPARATE OUTPUT
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2/5 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Multiplexer or Switches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2 V表面贴装:YES
最长断开时间:42 ns最长接通时间:82 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

DG2042DQ-T1-E3 数据手册

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DG2041, DG2042, DG2043  
Vishay Siliconix  
Low-Voltage, Low R Quad SPST Analog Switch  
ON  
FEATURES  
DESCRIPTION  
Halogen-free according to IEC 61249-2-21  
Definition  
The DG2041/2042/2043 are quad single-pole/single-throw  
monolithic CMOS analog switch designed for high  
performance switching of analog signals. Combining low  
power, fast switching, low on-resistance (RDS(on): 1 at  
2.7 V) and small physical size, the DG2041/2042/2043 are  
ideal for portable and battery powered applications requiring  
high performance and efficient use of board space.  
Low Voltage Operation (1.8 V to 5.5 V)  
Low On-Resistance - RDS(on): 1   
Fast Switching - 14 ns tON  
Low Charge Injection - QINJ: 1 pC  
Low Power Consumption  
TTL/CMOS Compatible  
The DG2041/2042/2043 are built on Vishay Siliconix’s new  
high density low voltage process. An epitaxial layer prevents  
TSSOP-16 and QFN-16 Packages  
Compliant to RoHS Directive 2002/95/EC  
latchup.  
Each switch conducts equally well in both directions when  
on, and blocks up to the power supply level when off.  
BENEFITS  
Reduced Power Consumption  
Simple Logic Interface  
High Accuracy  
Reduce Board Space  
APPLICATIONS  
Cellular Phones  
Communication Systems  
Portable Test Equipment  
Battery Operated Systems  
Sample and Hold Circuits  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION - DG2041  
DG2041DN  
QFN-16 (4 x 4)  
DG2041DQ  
TSSOP  
16  
15  
14  
13  
IN2  
IN1  
COM1  
NC1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
NC1  
N.C.  
GND  
NC4  
NC2  
V+  
1
2
3
4
12  
11  
10  
9
COM2  
NC2  
V+  
N.C.  
Top View  
Top View  
N.C.  
NC3  
GND  
NC4  
N.C.  
NC3  
COM4  
10 COM3  
IN4  
9
IN3  
5
6
7
8
TRUTH TABLE - DG2041  
Logic  
Switch  
On  
0
1
Off  
Switches Shown for Logic “0” Input  
Document Number: 72091  
S11-1185-Rev. B, 13-Jun-11  
www.vishay.com  
1
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  

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