DG201A, DG202
Data Sheet
May 2001
File Number 3117.3
Quad SPST, CMOS Analog Switches
Features
The DG201A and DG202 quad SPST analog switches are
designed using Intersil’s 44V CMOS process. These
• Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . 15V
• Low r (Max). . . . . . . . . . . . . . . . . . . . . . . . . . 175Ω
itle
DS(ON)
G20 bidirectional switches are latch-proof and feature break-
• TTL, CMOS Compatible
before-make switching. Designed to block signals up to
,
30V
in the OFF state, the DG201A and DG202 offer the
P-P
202
• Latch-Up Proof
advantages of low ON resistance (≤175Ω), wide input signal
range ( 15V) and provide both TTL and CMOS compatibility.
• True Second Source
b-
• Maximum Supply Ratings . . . . . . . . . . . . . . . . . . . . . 44V
• Logic Inputs Accept Negative Voltages
The DG201A and DG202 are specification and pinout
compatible with the industry standard devices.
t
uad
ST,
OS
Part Number Information
Functional Block Diagrams
DG201A
TEMP.
PKG.
NO.
a-
o
PART NUMBER RANGE ( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
S
1
DG201AAK
DG201ABK
DG201ACJ
DG201ACY
DG202AK
DG202CJ
-55 to 125
-25 to 85
0 to 70
F16.3
IN
IN
IN
1
itch
D
1
F16.3
E16.3
M16.3
F16.3
E16.3
S
2
utho
)
ey-
rds
ter-
2
3
D
2
0 to 70
16 Ld SOIC
S
3
-55 to 125
0 to 70
16 Ld CERDIP
16 Ld PDIP
D
3
S
4
IN
4
rpo-
ion,
i-
Pinout
D
4
DG201A, DG202
(CERDIP, PDIP, SOIC)
TOP VIEW
DG202
n-
ctor,
itch
OS
PST,
DT,
ST,
DT,
eo,
ET,
alog
itch,
an-
l)
S
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
IN
IN
2
1
IN
IN
IN
IN
1
2
3
4
D
S
D
2
1
1
D
1
S
2
S
2
V+ (SUB-
V-
-
STRATE)
GND
NC
D
S
2
S
4
S
3
3
D
4
D
3
D
3
IN
IN
4
3
S
4
D
4
SWITCHES SHOWN FOR LOGIC “1” INPUT
TRUTH TABLE
re-
LOGIC
DG201A
ON
DG202
OFF
0
1
OFF
ON
Logic “0” ≤0.8V, Logic “1” ≥ 2.4V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
1