Datasheet > DFPDIV

DFPDIV

更新时间： 2024-09-24 03:29:27

品牌	Logo	应用领域
DCD		/
页数	文件大小	规格书
3页	124K
描述
Floating Point Pipelined Divider Unit

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数据手册

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DFPDIV 数据手册

DFPDIV

Floating Point Pipelined Divider Unit

ver 2.15

● Fully synthesizable, static synchronous

O V E R V I E W

design with no internal tri-states

The DFPDIV uses the pipelined mathemat-

ics algorithm to divide two arguments. The

input numbers format is according to IEEE-

754 standard. DFPDIV supports single preci-

sion real number. Divide operation was pipe-

lined up to 15 levels. Input data are fed every

clock cycle. The first result appears after 15

clock periods latency and next results are

available each clock cycle. Full IEEE-754

precision and accuracy are included.

D E L I V E R A B L E S

Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

♦

◊ Active-HDL automatic simulation mac-

ros

A P P L I C A T I O N

● Math coprocessors

◊ NCSim automatic simulation macros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

Technical documentation

◊ Installation notes

● DSP algorithms

♦

● Embedded arithmetic coprocessor

● Data processing & control

◊ HDL core specification

◊ Datasheet

♦

Synthesis scripts

Example application

Technical support

K E Y F E A T U R E S

◊ IP Core implementation support

◊ 3 months maintenance

● Full IEEE-754 compliance

● Single precision real format support

● Simple interface

●

Delivery the IP Core updates, minor

and major versions changes

Delivery the documentation updates

Phone & email support

●

● No programming required

● 15 levels pipeline

L I C E N S I N G

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

● Full accuracy and precision

● Results available at every clock

● Overflow, underflow and invalid operation

Single Design license allows using IP Core in

single FPGA bitstream and ASIC implemen-

flags

● Fully configurable

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

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