Datasheet > DF6808

DF6808

更新时间： 2024-09-16 03:29:19

品牌	Logo	应用领域
DCD		微控制器
页数	文件大小	规格书
9页	237K
描述
8-bit FAST Microcontrollers Family

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DF6808 数据手册

DF6808

8-bit FAST Microcontrollers Family

ver 1.04

DF6808 IP Core especially attractive for

O V E R V I E W

automotive and battery-driven applications.

Document contains brief description of

DF6808 is fully customizable, which means

DF6808 core functionality. The DF6808 is a

it is delivered in the exact configuration to

advanced 8-bit MCU IP Core with highly so-

phisticated, on chip peripheral capabilities.

DF6808 soft core is binary-compatible with the

industry standard 68HC08 8-bit microcontrol-

ler and can achieve a performance 45-100

million instructions per second. There are

two configurations of DF6808: Harvard where

meet users requirements. There is no need to

pay extra for not used features and wasted

silicon. It includes fully automated testbench

with complete set of tests allowing easy

package validation at each stage of SoC de-

sign flow.

data and program buses are separated, and

C P U F E A T U R E S

● FAST architecture, 3.2 times faster than

von Neumann with common program and

data bus DF6808 has FAST architecture that

is 3.2 times faster compared to original im-

plementation. Core in standard configuration

has integrated on chip major peripheral func-

tion.

the original implementation

● Software compatible with industry standard

68HC08

● Configurable Harvard or Von Neumann

The DF6808 Microcontroller Core contains

full-duplex UART (Asynchronous serial com-

munications interface (SCI), and Synchronous

Serial Peripheral Interface SPI.

The main 16-bit, free-running timer system

has implemented two input capture lines and

two output-compare lines.

architectures

● 64 bytes of System Function Registers

space (SFRs)

● Up to 64 k bytes of Program Memory

● Up to 64k bytes of Data Memory

Self-monitoring circuitry is included on-chip to

protect against system errors. A computer

operating properly (COP) watchdog system

protects against software failures. An illegal

opcode detection circuit provides a non-

maskable interrupt if illegal opcode is de-

tected.

● De-multiplexed Address/Data Bus to allow

easy connection to memory

● Two power saving modes: STOP, WAI

● Ready pin allows Core to operate with slow

program and data memories

Two software-controlled power-saving modes,

WAIT and STOP, are available to conserve

additional power. These modes make the

● Fully synthesizable, static synchronous

design with no internal tri-states

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

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