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DES-011

更新时间: 2022-12-17 13:45:55
品牌 Logo 应用领域
智原科技 - FARADAY /
页数 文件大小 规格书
2页 129K
描述
SERIAL DIGITAL TO PARALLEL TTL MODULE

DES-011 数据手册

 浏览型号DES-011的Datasheet PDF文件第2页 
DES-011  
SERIAL DIGITAL TO PARALLEL TTL MODULE  
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Small compact design for pcb mounting  
Composite or Component digital inputs  
8 or 10 bit data  
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Auto 144,177,270, 360 mb/s Operation  
Automatic Cable equalisation  
+ 5V DC power  
Reclocked SD outputs available.  
This interface card accepts multistandard serial digital signals and converts these to a 10 bit parallel data stream with  
a word rate clock. In addition outputs indicating the presence of TRS and EAV timing reference signals are provided  
to allow easy decoding of the parallel data stream.  
Input Requirements  
Input data format  
Input data rates  
SMPTE 259M  
360 Mb/s serial 4:2:2 widescreen component  
270 Mb/s serial 4:2:2 component  
144,177 Mb/s serial NTSC/PAL  
75 ohm terminating  
Input Impedance  
Equalisation  
Automatic up to 40 dB at 200 MHz  
(Typically 300m of Belden 8281 at 270mb/s)  
Output Characteristics  
Parallel Output  
One parallel word at 14.4, 17.7, 27 or 36Mb/s  
TTL/CMOS levels.  
SD Outputs  
2 reclocked serial outputs, SMPTE 259M  
EAV Output  
End of active video flag. For component video, a logic low is  
output for one cycle of the parallel clock every time an EAV  
timing reference signal is detected. The pulse is aligned with  
the fourth word of the timing reference (the XYZ word.) For  
composite video, this line is always asserted high.  
TRS Output  
Timing reference flag.  
A logic low is output for the duration of the TRS.  
Other parameters  
Power  
Operating  
+5V ± 0.25V ( 300 mA max)  
00C to 400C  
Temperature  
Aqueous Washable  
Package  
No  
DR00174A  
ORDERING CODES  
DES-011A  
Reclocked o/p’s  
x
DES-011B  
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© Faraday Technology. As part of continual product improvement the specifications, details and dimensions shown in this publication are subject to change without notice  
FARA078d Page 1 of 2 Jan-00(B)  

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