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DDU8F-5010 PDF预览

DDU8F-5010

更新时间： 2024-11-23 06:52:51
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路输入元件
页数 文件大小 规格书
4页 44K
描述
5-TAP, TTL-INTERFACED FIXED DELAY LINE

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中文翻译

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DDU8F-5010 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP8,.3针数：8
Reach Compliance Code：compliant风险等级：5.16
Is Samacsys：N其他特性：INPUT TO 1ST TAP DELAY = 3.5+-1NS
系列：FJESD-30 代码：R-XDIP-T8
JESD-609代码：e3逻辑集成电路类型：ACTIVE DELAY LINE
功能数量：1抽头/阶步数：5
端子数量：8最高工作温度：70 °C
最低工作温度：输出极性：TRUE
封装主体材料：UNSPECIFIED封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：32 mA
可编程延迟线：NOProp。Delay @ Nom-Sup：10 ns
认证状态：Not Qualified座面最大高度：7.747 mm
子类别：Delay Lines最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子面层：TIN
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总延迟标称（td）：13.5 ns宽度：7.62 mm
Base Number Matches：1

DDU8F-5010 数据手册

 浏览型号DDU8F-5010的Datasheet PDF文件第2页浏览型号DDU8F-5010的Datasheet PDF文件第3页浏览型号DDU8F-5010的Datasheet PDF文件第4页 
DDU8F  
Ò
5-TAP, TTL-INTERFACED  
FIXED DELAY LINE  
(SERIES DDU8F)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
N/C  
T1  
N/C  
T3  
N/C  
T5  
IN  
N/C  
N/C  
T2  
N/C  
T4  
IN  
T2  
VCC  
·
·
·
·
·
·
Five equally spaced outputs  
Fits standard 8-pin DIP socket  
Low profile  
1
2
3
4
8
T1  
T3  
T5  
7
6
5
T4  
GND  
Auto-insertable  
8
GND  
Input & outputs fully TTL interfaced & buffered  
DDU8F-xx  
DDU8F-xxA1 Gull-Wing  
DDU8F-xxB1 J-Lead  
DIP  
10 T2L fan-out capability  
Military SMD  
DDU8F-xxMD1  
DDU8F-xxMD4  
DDU8F-xxM Military DIP  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The DDU8F-series device is a 5-tap digitally buffered delay line. The  
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an  
amount determined by the device dash number (See Table). For dash  
numbers less than 5025, the total delay of the line is measured from T1 to  
T5. The nominal tap-to-tap delay increment is given by one-fourth of the  
IN  
Signal Input  
T1-T5 Tap Outputs  
VCC +5 Volts  
GND Ground  
total delay, and the inherent delay from IN to T1 is nominally 3.5ns. For dash numbers greater than or  
equal to 5025, the total delay of the line is measured from IN to T5. The nominal tap-to-tap delay  
increment is given by one-fifth of this number.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
·
·
·
·
Minimum input pulse width: 40% of total delay  
Output rise time: 2ns typical  
Supply voltage: 5VDC ± 5%  
Supply current: ICCL = 32ma typical  
ICCH = 7ma typical  
Part  
Total  
Delay (ns)  
4 ± 1.0 *  
6 ± 1.0 *  
8 ± 2.0 *  
10 ± 2.0 *  
12 ± 2.0 *  
16 ± 2.0 *  
20 ± 3.0 *  
25 ± 3.0  
Delay Per  
Tap (ns)  
1.0 ± 0.5  
1.5 ± 0.5  
2.0 ± 1.0  
2.5 ± 1.0  
3.0 ± 1.0  
4.0 ± 1.5  
5.0 ± 2.0  
5.0 ± 2.0  
6.0 ± 2.0  
7.0 ± 2.0  
8.0 ± 2.0  
9.0 ± 3.0  
10.0 ± 3.0  
12.0 ± 3.0  
15.0 ± 3.0  
20.0 ± 3.0  
25.0 ± 3.0  
30.0 ± 3.0  
35.0 ± 4.0  
40.0 ± 4.0  
50.0 ± 5.0  
Number  
DDU8F-5004  
DDU8F-5006  
DDU8F-5008  
DDU8F-5010  
DDU8F-5012  
DDU8F-5016  
DDU8F-5020  
DDU8F-5025  
DDU8F-5030  
DDU8F-5035  
DDU8F-5040  
DDU8F-5045  
DDU8F-5050  
DDU8F-5060  
DDU8F-5075  
DDU8F-5100  
DDU8F-5125  
DDU8F-5150  
DDU8F-5175  
DDU8F-5200  
DDU8F-5250  
·
·
Operating temperature: 0° to 70° C  
Temp. coefficient of total delay: 100 PPM/°C  
30 ± 3.0  
35 ± 3.0  
40 ± 3.0  
45 ± 3.0  
50 ± 3.0  
60 ± 3.0  
75 ± 4.0  
100 ± 5.0  
125 ± 6.5  
150 ± 7.5  
175 ± 8.0  
200 ± 10.0  
250 ± 12.5  
3.5ns  
25%  
25%  
25%  
25%  
VCC IN  
T1  
T2  
T3  
T4  
T5 GND  
Functional diagram for dash numbers < 5025  
20%  
20%  
20%  
20%  
20%  
* Total delay is referenced to first tap output  
Input to first tap = 3.5ns ± 1ns  
VCC IN  
T1  
T2  
T3  
T4  
T5 GND  
Functional diagram for dash numbers >= 5025  
NOTE: Any dash number between 5004 and 5250  
not shown is also available.  
Ó1997 Data Delay Devices  
Doc #97012  
1/28/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

中文翻译

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