DDU8C
Ò
5-TAP, HCMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU8C)
data
delay
3
devices, inc.
FEATURES
PACKAGES
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
N/C
T1
N/C
T3
N/C
T5
IN
N/C
N/C
T2
N/C
T4
IN
T2
VDD
·
·
·
·
·
·
Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
1
2
3
4
8
T1
T3
T5
7
6
5
T4
GND
Auto-insertable
8
GND
Input & outputs fully CMOS interfaced & buffered
DDU8C-xx
DDU8C-xxA1 Gull-Wing
DDU8C-xxB1 J-Lead
DIP
10 T2L fan-out capability
Military SMD
DDU8C-xxMD1
DDU8C-xxMD4
DDU8C-xxM Military DIP
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU8C-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). The total
delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of the total delay.
IN
Signal Input
T1-T5 Tap Outputs
VDD +5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
SERIES SPECIFICATIONS
Part
Number
Total
Delay (ns)
50 ± 2.5
60 ± 3.0
Delay Per
Tap (ns)
·
·
·
·
Minimum input pulse width: 40% of total delay
Output rise time: 8ns typical
Supply voltage: 5VDC ± 5%
Supply current: ICCL = 40ma typical
ICCH = 10ma typical
Operating temperature: 0° to 70° C
Temp. coefficient of total delay: 300 PPM/°C
DDU8C-5050
DDU8C-5060
DDU8C-5075
DDU8C-5100
DDU8C-5125
DDU8C-5150
DDU8C-5175
DDU8C-5200
DDU8C-5250
10.0 ± 3.0
12.0 ± 3.0
15.0 ± 3.0
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.0
35.0 ± 4.0
40.0 ± 4.0
50.0 ± 5.0
75 ± 4.0
100 ± 5.0
125 ± 6.5
150 ± 7.5
175 ± 8.0
200 ± 10.0
250 ± 12.5
·
·
NOTE: Any dash number between 5004 and 5250
not shown is also available.
20%
20%
20%
20%
20%
VDD IN
T1
T2
T3
T4
T5 GND
DDU8C Functional diagram
Ó1997 Data Delay Devices
Doc #97013
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1/28/97
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