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DDU7C-100B3 PDF预览

DDU7C-100B3

更新时间： 2024-11-23 06:52:51
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路
页数 文件大小 规格书
4页 43K
描述
10-TAP, TTL-INTERFACED FIXED DELAY LINE

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中文翻译

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DDU7C-100B3 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：SOC,
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.73Is Samacsys：N
JESD-30 代码：R-XDSO-C16JESD-609代码：e3
逻辑集成电路类型：PASSIVE DELAY LINE功能数量：1
抽头/阶步数：10端子数量：16
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：UNSPECIFIED
封装代码：SOC封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
可编程延迟线：NO认证状态：Not Qualified
座面最大高度：8.89 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin (Sn)端子形式：C BEND
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总延迟标称（td）：100 ns
宽度：6.858 mmBase Number Matches：1

DDU7C-100B3 数据手册

 浏览型号DDU7C-100B3的Datasheet PDF文件第2页浏览型号DDU7C-100B3的Datasheet PDF文件第3页浏览型号DDU7C-100B3的Datasheet PDF文件第4页 
DDU7C  
Ò
10-TAP, TTL-INTERFACED  
FIXED DELAY LINE  
(SERIES DDU7C)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
IN  
T2  
VDD  
T1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
IN  
N/C  
T2  
VDD  
T1  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
·
·
·
·
·
·
Ten equally spaced outputs  
Fits standard 16-pin DIP socket  
Low profile  
T4  
T3  
T3  
T6  
T5  
T4  
T5  
T8  
T7  
Auto-insertable  
T6  
T7  
T10  
N/C  
GND  
T9  
Input & outputs fully CMOS interfaced & buffered  
T8  
T9  
N/C  
N/C  
10 T2L fan-out capability  
GND  
T10  
8
DDU7C-xx  
DDU7C-xxA3  
DDU7C-xxB3  
DIP  
Gull-Wing  
J-Lead  
Military DIP  
DDU7C-xxM  
DDU7F-xxMC3 Military SMD  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The DDU7C-series device is a 10-tap digitally buffered delay line. The  
signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by an  
amount determined by the device dash number. The nominal tap-to-tap  
delay increment is given by 1/10 of the dash number. For dash numbers  
less than 50, the total delay of the line is measured from T1 to T10, with the  
IN  
Signal Input  
T1-T10 Tap Outputs  
VDD +5 Volts  
GND Ground  
nominal value given by 9 times the increment. The inherent delay from IN to T1 is nominally 8.0ns. For  
dash numbers greater than or equal to 50, the total delay of the line is measured from IN to T10, with the  
nominal value given by the dash number.  
DASH NUMBER SPEC.’S  
SERIES SPECIFICATIONS  
Part  
Number  
Total  
Delay Per  
Tap (ns)  
2.5 ± 1.0  
10.0 ± 2.0  
15.0 ± 2.0  
20.0 ± 2.0  
25.0 ± 2.0  
30.0 ± 3.0  
40.0 ± 4.0  
50.0 ± 5.0  
·
·
·
·
Minimum input pulse width: 20% of total delay  
Output rise time: 8ns typical  
Supply voltage: 5VDC ± 5%  
Supply current: ICCL = 40ma typical  
ICCH = 10ma typical  
Operating temperature: 0° to 70° C  
Temp. coefficient of total delay: 300 PPM/°C  
Delay (ns)  
22.5 ± 2.0 *  
100 ± 5.0  
150 ± 7.5  
200 ± 10.0  
250 ± 12.5  
300 ± 15.0  
400 ± 20.0  
500 ± 25.0  
DDU7C-25  
DDU7C-100  
DDU7C-150  
DDU7C-200  
DDU7C-250  
DDU7C-300  
DDU7C-400  
DDU7C-500  
·
·
3.5ns  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
* Total delay is referenced to first tap  
Input to first tap = 8.0ns ± 2ns  
NOTE: Any dash number between 25 and  
500 not shown is also available.  
VCC IN  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9 T10 GND  
Functional diagram for dash numbers < 50  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
VCC IN  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9 T10 GND  
Functional diagram for dash numbers >= 50  
Ó1997 Data Delay Devices  
Doc #97019  
1/30/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

中文翻译

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