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DDU12H-1000MC3 PDF预览

DDU12H-1000MC3

更新时间： 2024-11-14 10:01:51
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路
页数 文件大小 规格书
4页 38K
描述
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H)

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中文翻译

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DDU12H-1000MC3 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
JESD-30 代码：R-XDSO-G24长度：32.512 mm
逻辑集成电路类型：ACTIVE DELAY LINE功能数量：1
抽头/阶步数：10端子数量：24
输出特性：OPEN-EMITTER输出极性：TRUE
封装主体材料：UNSPECIFIED封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED可编程延迟线：NO
认证状态：Not Qualified座面最大高度：7.112 mm
表面贴装：YES技术：ECL
端子形式：GULL WING端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总延迟标称（td）：1000 nsBase Number Matches：1

DDU12H-1000MC3 数据手册

 浏览型号DDU12H-1000MC3的Datasheet PDF文件第2页浏览型号DDU12H-1000MC3的Datasheet PDF文件第3页浏览型号DDU12H-1000MC3的Datasheet PDF文件第4页 
DDU12H  
Ò
5-TAP, ECL-INTERFACED  
FIXED DELAY LINE  
(SERIES DDU12H)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
GND  
GND  
1
32  
31  
30  
29  
T1  
·
·
·
Ten equally spaced outputs  
Fits in 300 mil 32-pin DIP socket  
Input & outputs fully 10KH-ECL interfaced & buffered  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
GND  
T1  
T3  
GND  
T2  
T4  
T2  
T4  
IN  
T3  
3
4
5
T5  
T5  
IN  
N/C  
N/C  
GND  
N/C  
N/C  
T6  
N/C  
VEE  
GND  
N/C  
N/C  
T7  
VEE  
8
9
9
GND  
GND  
T6  
24  
23  
10  
11  
12  
T8  
T10  
T8  
VEE  
T2  
T4  
T8  
11 22  
12 21  
T10  
DDU12H-xx DIP  
DDU12H-xxC3 SMD  
DDU12H-xxM Military DIP  
DDU12H-xxMC3 Mil SMD  
VEE  
16  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The DDU12H-series device is a 10-tap digitally buffered delay line. The  
signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by  
an amount determined by the device dash number (See Table). For dash  
numbers less than 20, the total delay of the line is measured from T1 to  
T10. The nominal tap-to-tap delay increment is given by one-ninth of the  
IN  
T1-T10 Tap Outputs  
VEE -5 Volts  
GND Ground  
Signal Input  
total delay, and the inherent delay from IN to T1 is nominally 1.5ns. For dash numbers greater than or  
equal to 20, the total delay of the line is measured from IN to T10. The nominal tap-to-tap delay increment  
is given by one-tenth of this number.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
Part  
Number  
Total  
Delay (ns)  
9 ± 1.0 *  
20 ± 2.0  
25 ± 2.0  
40 ± 2.0  
50 ± 2.5  
75 ± 4.0  
100 ± 5.0  
150 ± 7.5  
200 ± 10.0  
250 ± 12.5  
300 ± 15.0  
400 ± 20.0  
500 ± 25.0  
750 ± 37.5  
1000 ± 50.0  
1500 ± 75.0  
Delay Per  
Tap (ns)  
1.0 ± 0.3  
2.0 ± 0.4  
2.5 ± 0.4  
4.0 ± 0.5  
5.0 ± 1.0  
7.5 ± 1.5  
10.0 ± 2.0  
15.0 ± 2.0  
20.0 ± 2.0  
25.0 ± 2.0  
30.0 ± 2.0  
40.0 ± 2.0  
50.0 ± 2.5  
75.0 ± 4.0  
100.0 ± 5.0  
150.0 ± 7.0  
·
·
·
·
·
·
Minimum input pulse width: 10% of total delay  
Output rise time: 2ns typical  
Supply voltage: -5VDC ± 5%  
Power dissipation: 400mw typical (no load)  
Operating temperature: -30° to 85° C  
Temp. coefficient of total delay: 100 PPM/°C  
DDU12H-10  
DDU12H-20  
DDU12H-25  
DDU12H-40  
DDU12H-50  
DDU12H-75  
DDU12H-100  
DDU12H-150  
DDU12H-200  
DDU12H-250  
DDU12H-300  
DDU12H-400  
DDU12H-500  
DDU12H-750  
DDU12H-1000  
DDU12H-1500  
1.5ns  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
VCC IN  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9 T10 GND  
Functional diagram for dash numbers < 20  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
10%  
* Total delay is referenced to first tap output  
Input to first tap = 1.5ns ± 1ns  
VCC IN  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9 T10 GND  
NOTE: Any dash number between 10 and 1500  
not shown is also available.  
Functional diagram for dash numbers >= 20  
Ó1997 Data Delay Devices  
Doc #97036  
12/11/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
1234

中文翻译

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