5秒后页面跳转
3D7503-30 PDF预览

3D7503-30

更新时间: 2024-02-24 17:33:19
品牌 Logo 应用领域
DATADELAY 解码器网络接口电信集成电路电信电路光电二极管编码器
页数 文件大小 规格书
5页 41K
描述
MONOLITHIC MANCHESTER ENCODER/DECODER

3D7503-30 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.8Is Samacsys:N
JESD-30 代码:R-PDIP-T14长度:19.305 mm
功能数量:1端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:4.58 mm标称供电电压:5 V
表面贴装:NO技术:CMOS
电信集成电路类型:MANCHESTER ENCODER/DECODER温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

3D7503-30 数据手册

 浏览型号3D7503-30的Datasheet PDF文件第2页浏览型号3D7503-30的Datasheet PDF文件第3页浏览型号3D7503-30的Datasheet PDF文件第4页浏览型号3D7503-30的Datasheet PDF文件第5页 
3D7503  
Ò
MONOLITHIC MANCHESTER  
ENCODER/DECODER  
(SERIES 3D7503)  
data  
3
delay  
devices, inc.  
PACKAGES  
FEATURES  
CIN  
CEN  
RX  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
·
·
·
·
·
·
·
·
·
·
All-silicon, low-power CMOS technology  
Encoder and decoder function independently  
Encoder has buffered clock output  
TTL/CMOS compatible inputs and outputs  
Vapor phase, IR and wave solderable  
Auto-insertable (DIP pkg.)  
Low ground bounce noise  
Maximum data rate: 50 MBaud  
Data rate range: ±15%  
CBUF  
LOOP  
TXENB  
DOUTB  
TXB  
COUT  
DIN  
RESB  
GND  
8
TX  
3D7503-xxx  
3D7503G-xxx Gull Wing (.300)  
3D7503D-xxx SOIC (.150)  
DIP (.300)  
Lock-in time: 1 bit  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
Encoder:  
The 3D7503 is a monolithic CMOS Manchester Encoder/Decoder combo  
chip. The device uses bi-phase-level encoding to embed a clock signal  
into a data stream for transmission across a communications link. In this  
encoding mode, a logic one is represented by a high-to-low transition in  
the center of the bit cell, while a logic zero is represented by a low-to-high  
transition.  
CIN  
DIN  
Clock Input  
Data Input  
RESB Reset  
CEN  
Clock buffer enable  
TXENB Transmit enable  
CBUF Buffered clock  
TX,TXB Transmitted signal  
The Manchester encoder combines the clock (CIN) and data (DIN) into a  
single bi-phase-level signal (TX). An inverted version of this signal (TXB)  
is also available. The data baud rate (in MBaud) is equal to the input  
clock frequency (in MHz). A replica of the clock input is also available  
(CBUF).  
Decoder:  
RX  
Received Signal  
COUT Recovered Clock  
DOUTB Recovered Data  
The encoder may be reset by setting the RESB input low; otherwise, it  
should be left high. The TX and TXB signals may be disabled (high-Z) by  
setting TXENB high. Similarly, CBUF may be disabled by setting CEN  
low. Under most operating conditions, the encoder is never reset, TX and  
TXB are always enabled, and CBUF is not used. With this in mind, the  
3D7503 provides an internal pull-up resistor on RESB and internal pull-  
Common:  
LOOP Loop enable  
VDD  
GND  
+5 Volts  
Ground  
down resistors on CEN and TXENB, so that most users can leave these inputs uncommitted.  
The Manchester decoder accepts the embedded-clock signal at the RX input. The recovered clock and  
data signals are presented on COUT and DOUTB, respectively, with the data signal inverted. The  
operating baud rate (in MBaud) is specified by the dash number of the device. The input baud rate may  
vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the  
information received.  
Because the decoder is not PLL-based, it does not require a long preamble in order to lock onto the  
received signal. Rather, the device requires at most one bit cell before the data presented at the output is  
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise  
turned off.  
Normally, the encoder and decoder function independently. However, if the LOOP input is set high, the  
encoded TX signal is fed back internally into the decoder and the RX input is ignored. This feature is  
useful for diagnostics. The LOOP input has an internal pull-down resistor and may be left uncommitted if  
this feature is not needed.  
Ó1998 Data Delay Devices  
Doc #98009  
12/11/98  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

与3D7503-30相关器件

型号 品牌 描述 获取价格 数据表
3D7503-40 DATADELAY MONOLITHIC MANCHESTER ENCODER/DECODER

获取价格

3D7503-5 DATADELAY MONOLITHIC MANCHESTER ENCODER/DECODER

获取价格

3D7503-50 DATADELAY MONOLITHIC MANCHESTER ENCODER/DECODER

获取价格

3D7503D DATADELAY MONOLITHIC MANCHESTER ENCODER/DECODER

获取价格

3D7503D-10 DATADELAY Manchester Encoder/Decoder, CMOS, PDSO14, 0.150 INCH, SOIC-14

获取价格

3D7503D-20 DATADELAY MONOLITHIC MANCHESTER ENCODER/DECODER

获取价格