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3D3522D-10 PDF预览

3D3522D-10

更新时间: 2024-02-21 22:00:26
品牌 Logo 应用领域
DATADELAY 解码器网络接口电信集成电路电信电路光电二极管
页数 文件大小 规格书
4页 259K
描述
MONOLITHIC MANCHESTER DECODER

3D3522D-10 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.72Is Samacsys:N
JESD-30 代码:R-PDSO-G14长度:8.695 mm
功能数量:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.82 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:MANCHESTER DECODER温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

3D3522D-10 数据手册

 浏览型号3D3522D-10的Datasheet PDF文件第2页浏览型号3D3522D-10的Datasheet PDF文件第3页浏览型号3D3522D-10的Datasheet PDF文件第4页 
3D3522  
MONOLITHIC MANCHESTER  
DECODER  
ata  
(SERIES 3D3522)  
FEATURES  
PACKAGES  
All-silicon, low-power CMOS  
RX  
N/C  
N/C  
CLK  
N/C  
N/C  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
N/C  
technology  
3.3V operation  
N/C  
N/C  
N/C  
N/C  
CMOS compatible inputs and  
outputs  
RX  
CLK  
N/C  
1
2
3
4
8
7
6
5
VDD  
N/C  
N/C  
Vapor phase, IR and wave  
solderable  
Auto-insertable (DIP pkg.)  
Low ground bounce noise  
Maximum data rate: 50 MBaud  
Data rate range: ±15%  
GND  
8
DATB  
GND  
DATB  
3D3522-xxx  
DIP (.300)  
3D3522M-xxx DIP (.300)  
3D3522G-xxx Gull Wing (.300)  
3D3522D-xxx SOIC (.150)  
3D3522H-xxx Gull Wing (.300)  
3D3522Z-xxx SOIC (.150)  
For mechanical dimensions, click here.  
For package marking details, click here.  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D3522 product family consists of monolithic CMOS Manchester  
Decoders. The unit accepts at the RX input a bi-phase-level,  
embedded-clock signal. In this encoding mode, a logic one is  
represented by a high-to-low transition within the bit cell, while a logic  
zero is represented by a low-to-high transition. The recovered clock  
and data signals are presented on CLK and DATB, respectively, with  
RX  
Signal Input  
CLK  
Signal Output (Clock)  
DATB Signal Output (Data)  
VDD +3.3 Volts  
GND Ground  
the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input  
baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the  
integrity of the information received.  
Because the 3D3522 is not PLL-based, it does not require a long preamble in order to lock onto the  
received signal. Rather, the device requires at most one bit cell before the data presented at the output is  
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise  
turned off.  
The all-CMOS 3D3522 integrated circuit has been designed as a reliable, economic alternative to hybrid  
Manchester Decoders. It is CMOS-compatible and is offered in standard 8-pin and 14-pin auto-insertable  
DIPs and space saving surface mount 8-pin and 14-pin SOICs.  
TABLE 1: PART NUMBER SPECIFICATIONS  
PART  
BAUD RATE (MBaud)  
NUMBER  
3D3522-0.5  
3D3522-1  
Nominal  
Minimum  
0.43  
Maximum  
0.50  
1.00  
5.00  
0.57  
1.15  
0.85  
3D3522-5  
4.25  
5.75  
3D3522-10  
3D3522-20  
3D3522-25  
3D3522-50  
10.00  
20.00  
25.00  
50.00  
8.50  
11.50  
23.00  
28.75  
57.50  
17.00  
21.25  
42.50  
NOTES: Any baud rate between 0.5 and 50 MBaud not shown is also available at no extra cost.  
2006 Data Delay Devices  
Doc #06005  
5/8/2006  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  

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