DS1100L
3.3V 5-Tap Economy Timing
Element (Delay Line)
www.maxim-ic.com
PIN ASSIGNMENT
FEATURES
C All-Silicon Timing Circuit
C Five Taps Equally Spaced
C Delays are Stable and Precise
C Both Leading- and Trailing-Edge Accuracy
C 3.3V Version of the DS1100
C Low-Power CMOS
IN
TAP 2
TAP 4
GND
1
2
3
4
8
7
6
5
VCC
TAP 1
TAP 3
TAP 5
C TTL-/CMOS-compatible
C Vapor-Phase and IR Solderable
C Custom Delays Available
C Fast-Turn Prototypes
DS1100LZ SO (150mil)
DS1100LU µSOP
C Delays Specified Over Both Commercial and
Industrial Temperature Ranges
PIN DESCRIPTION
TAP 1 to TAP 5
- TAP Output Number
- +3.3V
VCC
GND
IN
- Ground
- Input
DESCRIPTION
The DS1100L is a 3.3V version of the DS1100. It is characterized for operation over the range 3.0V to
3.6V. The DS1100L series delay lines have five equally spaced taps providing delays from 4ns to 500ns.
These devices are offered in surface-mount packages to save PC board area. Low cost and superior
reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and
industry-standard µSOP and SO packaging. The DS1100L 5-tap silicon delay line reproduces the input-
logic state at the output after a fixed delay as specified by the extension of the part number after the dash.
The DS1100L is designed to reproduce both leading and trailing edges with equal precision. Each tap is
capable of driving up to ten 74LS loads.
Dallas Semiconductor can customize standard products to meet special needs.
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