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DAC8228

更新时间: 2024-11-29 11:11:23
品牌 Logo 应用领域
德州仪器 - TI 转换器数模转换器
页数 文件大小 规格书
59页 1994K
描述
八路、低功耗、14 位、+/-16.5V 输出并行输入数模转换器

DAC8228 数据手册

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DAC8228  
www.ti.com  
SBAS462A JUNE 2009REVISED NOVEMBER 2009  
Octal, 14-Bit, Low-Power, High-Voltage Output, Parallel Input  
DIGITAL-TO-ANALOG CONVERTER  
Check for Samples: DAC8228  
1
FEATURES  
DESCRIPTION  
2
Bipolar Output: ±3V, up to ±16.5V  
The DAC8228 is  
digital-to-analog converter (DAC). With  
a
low-power, octal, 14-bit  
5V  
a
Unipolar Output: 0V to +33V  
14-Bit Resolution  
reference, the output can either be a bipolar ±15V  
voltage when operating from a dual ±15.5V (or  
higher) power supply, or a unipolar 0V to +30V  
voltage when operating from a +30.5V power supply.  
With a 5.5V reference, the output can be ±16.5V for a  
dual ±17V (or higher) power supply, or a unipolar 0V  
to +33V voltage when operating from a +33.5V (or  
higher) power supply. This DAC provides low-power  
operation, good linearity, and low glitch over the  
specified temperature range of –40°C to +105°C. This  
device is trimmed in manufacturing and has very low  
zero and full-scale error. In addition, user calibration  
can be performed to achieve ±1 LSB bipolar  
zero/full-scale error for a bipolar supply, or ±1 LSB  
zero-code/full-scale error for a unipolar supply over  
the entire signal chain. The output range can be  
offset by using the DAC Offset Register.  
Low Power: 13.5mW/Ch  
Relative Accuracy: 1LSB Max  
Flexible User Calibration  
Low Zero/Full-Scale Error  
Before User Calibration: ±2.5 LSB Max  
After User Calibration: ±1 LSB  
Low Glitch: 4nV-s  
Settling Time: 15μs  
Channel Monitor Output  
Programmable Gain: x4, x6  
Programmable Offset  
14-Bit Parallel Interface:  
50MHz (Write Operation)  
The DAC8228 features a standard, high-speed, 14-bit  
parallel interface that operates at up to 50MHz and is  
1.8V, 3V, and 5V logic compatible, to communicate  
with a DSP or microprocessor. The eight DACs and  
the auxiliary registers are addressed with five address  
lines. The device features double-buffered interface  
logic. An asynchronous load input (LDAC) transfers  
data from the DAC data register to the DAC latch.  
The asynchronous CLR input sets the output of all  
eight DACs to AGND. The VMON pin is a monitor  
output that connects to the individual analog outputs,  
the offset DAC, and the reference buffer outputs  
through a multiplexer (mux).  
Packages: QFN-56 (8mm x 8mm),  
TQFP-64 (10mm x 10mm)  
APPLICATIONS  
Automatic Test Equipment  
PLC and Industrial Process Control  
Communications  
IOVDD  
DGND  
DVDD  
AVDD  
AVSS  
REF-A  
Analog Monitor  
DAC8228  
VOUT-0  
VOUT-7  
VMON  
Reference  
Buffer A  
OFFSET  
DAC A  
A0  
Ref Buffer A  
The DAC8228 is pin-to-pin compatible with the  
DAC8728 (16-bit) and the DAC7728 (12-bit).  
Command  
Registers  
Ref Buffer B  
OFFSET-B  
A4  
R/W  
CS  
To DAC-0, DAC-1,  
DAC-2, DAC-3  
(When Correction Engine Disabled)  
OFFSET-A  
VOUT-0  
D0  
DAC-0  
Input Data  
Register 0  
Correction  
Engine  
DAC-0  
Data  
Latch-0  
D13  
To DAC-0, DAC-1,  
DAC-2, DAC-3  
LDAC  
User Calibration:  
Zero Register 0  
Gain Regsiter 0  
Internal Trimming  
Zero/Gain; INL  
RST  
AGND-A  
RSTSEL  
LDAC  
To DAC-4, DAC-5, DAC-6, DAC-7  
CLR  
USB/BTC  
BUSY  
OFFSET-B  
VOUT-7  
(Same Function Blocks  
for All Channels)  
Reference  
Buffer B  
OFFSET  
DAC B  
GPIO  
Power-Up/  
Power-Down  
Control  
AGND-B  
REF-B  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  

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