DAC1008D650

更新时间： 2024-01-18 20:45:08

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
98页	2645K
描述
Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

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DAC1008D650 技术参数

生命周期：	Transferred	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.7
Is Samacsys：	N	最大模拟输出电压：	3.47 V
最小模拟输出电压：	1.8 V	转换器类型：	D/A CONVERTER
输入位码：	OFFSET BINARY, 2'S COMPLEMENT BINARY	输入格式：	SERIAL
JESD-30 代码：	S-PQCC-N64	长度：	9 mm
位数：	10	功能数量：	1
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1 mm	标称安定时间 (tstl)：	0.02 µs
标称供电电压：	1.8 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	9 mm	Base Number Matches：	1

DAC1008D650 数据手册

DAC1008D650

Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating

with JESD204A interface

Rev. 1 — 1 October 2010

Preliminary data sheet

1. General description

The DAC1008D650 is a high-speed 10-bit dual channel Digital-to-Analog Converter

(DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA

transmitters.

Because of its digital on-chip modulation, the DAC1008D650 allows the complex pattern

provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to

IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit

Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.

The DAC1008D650 also includes a 2×, 4× or 8× clock multiplier which provides the

appropriate internal clocks and an internal regulation to adjust the output full-scale

current.

The input data format is serial according to JESD204A specification. This new interface

has numerous advantages over the traditional parallel one: easy PCB layout, lower

radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum

number of lanes of the DAC1008D650 is 4 and its maximum serial data rate is

3.125 Gbps.

The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output

clock period between several DAC devices. MDS incorporates modes: Master/slave and

All slave mode.

2. Features and benefits

Dual 10-bit resolution

IMD3: 76 dBc; f_s= 640 Msps;

f_o= 140 MHz

650 Msps maximum update rate

ACPR: 64 dBc; two carriers WCDMA;

f_s= 640 Msps; f_o= 133 MHz

Selectable 2×, 4× or 8× interpolation

Typical 1.20 W power dissipation at

4× interpolation, PLL off and 640 Msps

filters

Input data rate up to 312.5 Msps

Power-down mode and Sleep modes

Very low noise cap free integrated PLL Differential scalable output current from

1.6 mA to 22 mA

32-bit programmable NCO frequency

Four JESD204A serial input lanes

On-chip 1.25 V reference

External analog offset control

(10-bit auxiliary DACs)

1.8 V and 3.3 V power supplies

LVDS compatible clock inputs

Internal digital offset control

Inverse (sin x) / x function

12 3 4 5 6 7...98

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与DAC1008D650相关器件

型号	品牌	描述	获取价格	数据表
DAC1008D650_1012	NXP	Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8×	获取价格
DAC1008D650HN	NXP	Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8×	获取价格
DAC1008D650HN	IDT	D/A Converter	获取价格
DAC1008D750	NXP	Dual 10-bit DAC up to 750 Msps 2×, 4× or 8× i	获取价格
DAC1008D750_11	NXP	Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8×	获取价格
DAC1008D750HN	NXP	Dual 10-bit DAC up to 750 Msps 2×, 4× or 8× i	获取价格

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