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DA9080 PDF预览

DA9080

更新时间: 2024-11-08 14:58:15
品牌 Logo 应用领域
瑞萨 - RENESAS 集成电源管理电路
页数 文件大小 规格书
53页 644K
描述
Highly Integrated PMIC with 4 Bucks, 1 LDO & 8-Bit ADC in a QFN Package

DA9080 数据手册

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DA9080  
High Current, Highly Configurable System  
PMIC with Four Bucks and One LDO  
General Description  
DA9080 is a five-channel advanced, configurable, system power management IC (PMIC) with four  
buck regulators and one LDO. This highly integrated, flexible PMIC is capable of up to 10 A of output  
current. The output voltage of the regulators can be programmed and sequenced based on the  
application needs. The DA9080 also integrates an 8-bit ADC, along with several other features, that  
simplifies overall system design. Dynamic voltage control (DVC), robust protection features, and a  
dedicated I2C interface that supports multiple modes extend the applicability of this device to a wide  
range of end applications.  
The high-efficiency, fast transient response, and small footprint of the DA9080 lends itself to become  
the preferred power solution for a host of complex, high-performance applications. The DA9080 is  
offered in a QFN package.  
Key Features  
Power supply voltage (VIN) 4.0 V to 5.5 V  
Four buck converters  
General purpose ADC:  
8-bit SAR ADC  
Selectable output voltage range for bucks:  
Two external inputs  
Die temperature sense  
CH1 Buck: 2.1 V to 3.3 V, 20 mV step  
CH2 Buck: 1.5 V to 2.6 V, 20 mV step  
Protection functions:  
CH3 Buck: 0.9 V to 1.3 V, 5 mV step  
(supports 1.35 V and 1.8 V)  
Over-current protection  
Over/under-voltage protection  
Thermal shutdown protection  
CH4 Buck: 0.8 V to 1.4 V, 5 mV step  
Maximum output current:  
I2C control interface:  
CH1, CH2, and CH3 Buck: 1.5 A  
CH4 Buck: 5.0 A  
Standard mode (100 kbit/s)  
Fast mode (400 kbit/s)  
Fast mode+ (1 Mbit/s)  
Interleaving of switching phases of bucks  
LDO:  
Package: 32 lead QFN, 5.0 mm x 5.0 mm  
VOUT: 3.3 V, IOUT: 0.2 A (max)  
Applications  
Client and Enterprise SSD modules  
Embedded Computing  
Integrated Microcontroller Internet of Things  
DSPs or FPGAs with Peripherals  
System Diagram  
BUCK1  
BUCK2  
3.3V_SYS  
1.8V_SYS  
VDD_CORE_SOC  
VDD_IO_SOC  
BUCK4  
SoC  
VDD_ANA_SOC  
DA9080  
VDD_IO_DDR  
VDD_DDR  
DDR  
BUCK3  
LDO  
VDD_AUD  
AUDIO  
Figure 1: System Diagram  
Datasheet  
Revision 3.1  
23-Nov-2023  
CFR0011-120-00  
1 of 53  
© 2023 Renesas Electronics  
 
 
 
 
 

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