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D4564841G5 PDF预览

D4564841G5

更新时间: 2024-10-27 21:53:55
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器
页数 文件大小 规格书
85页 903K
描述
64M-bit Synchronous DRAM 4-bank, LVTTL

D4564841G5 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD4564441, 4564841, 4564163  
64M-bit Synchronous DRAM  
4-bank, LVTTL  
Description  
The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access  
memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively.  
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.  
All inputs and outputs are synchronized with the positive edge of the clock.  
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).  
These products are packaged in 54-pin TSOP (II).  
Features  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by A12 and A13 (Bank Select)  
Byte control (×16) by LDQM and UDQM  
Programmable Wrap sequence (Sequential / Interleave)  
Programmable burst length (1, 2, 4, 8 and full page)  
Programmable /CAS latency (2 and 3)  
Automatic precharge and controlled precharge  
CBR (auto) refresh and self refresh  
• ×4, ×8, ×16 organization  
Single 3.3 V ± 0.3 V power supply  
LVTTL compatible inputs and outputs  
4,096 refresh cycles / 64 ms  
Burst termination by Burst stop command and Precharge command  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0149N10 (Ver.1.0)  
(Previous No. M12621EJCV0DS00)  
Date Published August 2001 (K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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