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CYW15G0403DXB-BGC

更新时间： 2024-11-28 03:10:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
45页 1145K
描述
Independent Clock Quad HOTLink II⑩ Transceiver

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CYW15G0403DXB-BGC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：HBGA, BGA256,20X20,50
针数：256Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.83
数据速率：1500000 MbpsJESD-30 代码：S-PBGA-B256
JESD-609代码：e0长度：27 mm
湿度敏感等级：3功能数量：1
端子数量：256收发器数量：4
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：HBGA
封装等效代码：BGA256,20X20,50封装形状：SQUARE
封装形式：GRID ARRAY, HEAT SINK/SLUG峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.745 mm子类别：Network Interfaces
最大压摆率：1.32 mA标称供电电压：3.3 V
表面贴装：YES技术：BICMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：27 mm
Base Number Matches：1

CYW15G0403DXB-BGC 数据手册

 浏览型号CYW15G0403DXB-BGC的Datasheet PDF文件第2页浏览型号CYW15G0403DXB-BGC的Datasheet PDF文件第3页浏览型号CYW15G0403DXB-BGC的Datasheet PDF文件第4页浏览型号CYW15G0403DXB-BGC的Datasheet PDF文件第5页浏览型号CYW15G0403DXB-BGC的Datasheet PDF文件第6页浏览型号CYW15G0403DXB-BGC的Datasheet PDF文件第7页 
CYP15G0403DXB  
CYV15G0403DXB  
CYW15G0403DXB  
Independent Clock Quad HOTLink II™  
Transceiver  
• Per-channel Link Quality Indicator  
Features  
— Analog signal detect  
• Second-generation HOTLink® technology  
• Compliant to multiple standards  
— Digital signal detect  
• Low-power 3W @ 3.3V typical  
— ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M, Fibre  
Channel and Gigabit Ethernet (IEEE802.3z)  
• Single 3.3V supply  
• 256-ball thermally enhanced BGA  
• Pb-Free package option available  
• 0.25μ BiCMOS technology  
— CPRI™ compliant  
— CYW15G0403DXB compliant to OBSAI-RP3  
— 8B/10B coded data or 10 bit uncoded data  
Functional Description  
• Quad channel transceiver operates from 195 to  
1500 MBaud serial data rate  
The CYP(V)15G0403DXB[1] Independent Clock Quad  
HOTLink II™ Transceiver is a point-to-point or point-to-multi-  
point communications building block enabling transfer of data  
over a variety of high-speed serial links like optical fiber,  
balanced, and unbalanced copper transmission lines. The  
signaling rate can be anywhere in the range of 195 to 1500  
MBaud per serial link. Each channel operates independently  
with its own reference clock allowing different rates. Each  
transmit channel accepts parallel characters in an Input  
Register, encodes each character for transport, and then  
converts it to serial data. Each receive channel accepts serial  
data and converts it to parallel data, decodes the data into  
characters, and presents these characters to an Output  
Register. Figure 1 on page 2 illustrates typical connections  
between independent host systems and corresponding  
CYP(V)(W)15G0403DXB chips  
— CYW15G0403DXB operates from 195 to 1540 MBaud  
— Aggregate throughput of up to 12 Gbits/second  
• Second-generation HOTLink technology  
• Truly independent channels  
— Each channel can operate at a different signaling rate  
— Each channel can transport a different type of data  
• Selectable input/output clocking options  
• Internal phase-locked loops (PLLs) with no external PLL  
components  
• Dual differential PECL-compatible serial inputs per channel  
• Internal DC-restoration  
• Dual differential PECL-compatible serial outputs per  
channel  
The CYW15G0403DXB[1] operates from 195 to 1540 MBaud,  
which includes operation at the OBSAI RP3 datarate of both  
1536 MBaud and 768 MBaud.  
— Source matched for 50Ω transmission lines  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
• MultiFrame™ Receive Framer provides alignment options  
— Bit and byte alignment  
The CYV15G0403DXB satisfies the SMPTE-259M and  
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-  
logical Test Requirements.  
As  
a
second-generation  
HOTLink  
device,  
the  
CYP(V)(W)15G0403DXB extends the HOTLink family with  
enhanced levels of integration and faster data rates, while  
maintaining serial-link compatibility (data, command, and  
BIST) with other HOTLink devices. The transmit (TX) section  
of the CYP(V)(W)15G0403DXB Quad HOTLink II consists of  
four independent byte-wide channels. Each channel can  
accept either 8-bit data characters or preencoded 10-bit trans-  
mission characters. Data characters may be passed from the  
Transmit Input Register to an integrated 8B/10B Encoder to  
improve their serial transmission characteristics. These  
encoded characters are then serialized and output from dual  
Positive ECL (PECL) compatible differential transmission-line  
drivers at a bit-rate of either 10 or 20 times the input reference  
clock for that channel.  
— Comma or Full K28.5 detect  
— Single or Multi-byte Framer for byte alignment  
— Low-latency option  
• Synchronous LVTTL parallel interface  
• JTAG boundary scan  
• Built-In Self-Test (BIST) for at-speed link testing  
• Compatible with  
— Fiber-optic modules  
— Copper cables  
— Circuit board traces  
.
Note  
1. CYV15G0403DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0403DXB refers to OBSAI RP3 compliant devices (maximum operating  
data rate is 1540 MBaud). CYP15G0403DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI  
RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0403DXB refers to all three devices.  
Cypress Semiconductor Corporation  
Document #: 38-02065 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 2, 2007  
[+] Feedback  
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