CYW15G0401DXB

更新时间： 2024-11-28 03:10:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
53页	571K
描述
Quad HOTLink II⑩ Transceiver

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数据手册

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CYW15G0401DXB 数据手册

CYP15G0401DXB

CYV15G0401DXB

CYW15G0401DXB

Quad HOTLink II™ Transceiver

• Internal phase-locked loops (PLLs) with no external

PLL components

Features

• Second-generation HOTLink^®technology

• Dual differential PECL-compatible serial inputs per

channel

— Internal DC-restoration

• Compliant to multiple standards

— ESCON, DVB-ASI, Fibre Channel and Gigabit

Ethernet (IEEE802.3z)

• Dual differential PECL-compatible serial outputs per

channel

—CPRI™ compliant

— Source matched for 50Ω transmission lines

— No external bias resistors required

— Signaling-rate controlled edge-rates

• Compatible with

—fiber-optic modules

— copper cables

— circuit board traces

• JTAG boundary scan

• Built-In Self-Test (BIST) for at-speed link testing

• Per-channel Link Quality Indicator

— Analog signal detect

— Digital signal detect

• Low power 2.5W @ 3.3V typical

• Single 3.3V supply

• 256-ball thermally enhanced BGA

• Pb-free package option available

• 0.25µ BiCMOS technology

— CYW15G0401DXB compliant to OBSAI-RP3

— CYV15G0401DXB compliant to SMPTE 259M and

SMPTE 292M

—8B/10B encoded or 10-bit unencoded data

• Quad channel transceiver operates from 195 to

1500 MBaud serial data rate

— CYW15G0401DXB operates from 195 to 1540 MBaud

— Aggregate throughput of 12 GBits/second

• Selectable parity check/generate

• Selectable multi-channel bonding options

— Four 8-bit channels

—Two 16-bit channels

— One 32-bit channel

— N x 32-bit channel support (inter-chip)

• Skew alignment support for multiple bytes of offset

• Selectable input/output clocking options

• MultiFrame™ Receive Framer

— Bit and Byte alignment

—Comma or full K28.5 detect

—Single- or multi-byte framer for byte alignment

— Low-latency option

Functional Description

The CYP(V)15G0401DXB^[1]Quad HOTLink II™ Transceiver

is a point-to-point or point-to-multipoint communications

building block allowing the transfer of data over high-speed

serial links (optical fiber, balanced, and unbalanced copper

transmission lines) at signaling speeds ranging from

195-to-1500 MBaud per serial link.

• Synchronous LVTTL parallel interface

• Optional Elasticity Buffer in Receive Path

• Optional Phase Align Buffer in Transmit Path

Serial Links

Backplane or

Cabled

Connections

Figure 1. HOTLink II System Connections

Note:

1. CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0401DXB refers to OBSAI RP3 compliant devices (maximum

operating data rate is 1540 MBaud). CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and

also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0401DXB refers to all three devices.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-02002 Rev. *L

Revised March 30, 2005

12 3 4 5 6 7...53

中文翻译

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与CYW15G0401DXB相关器件

型号	品牌	获取价格	描述	数据表
CYW15G0401DXB-BGC	CYPRESS	获取价格	Quad HOTLink II⑩ Transceiver
CYW15G0401DXB-BGI	CYPRESS	获取价格	Quad HOTLink II⑩ Transceiver
CYW15G0401DXB-BGXC	CYPRESS	获取价格	Quad HOTLink II⑩ Transceiver
CYW15G0401DXB-BGXI	CYPRESS	获取价格	Quad HOTLink II⑩ Transceiver
CYW15G0403DXB	CYPRESS	获取价格	Independent Clock Quad HOTLink II⑩ Transceive
CYW15G0403DXB-BGC	CYPRESS	获取价格	Independent Clock Quad HOTLink II⑩ Transceive
CYW15G0403DXB-BGI	CYPRESS	获取价格	Independent Clock Quad HOTLink II⑩ Transceive
CYW15G0403DXB-BGXC	CYPRESS	获取价格	Independent Clock Quad HOTLink II⑩ Transceive
CYW15G0403DXB-BGXI	CYPRESS	获取价格	Independent Clock Quad HOTLink II⑩ Transceive
CYW173SXC	SILICON	获取价格	Clock Generator, 50MHz, CMOS, PDSO16, 0.150 INCH, LEAD FREE, SOIC-16

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