CYV15G0101DXB

更新时间： 2024-11-24 22:09:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
39页	456K
描述
Single-channel HOTLink Transceiver

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CYV15G0101DXB 数据手册

CYP15G0101DXB

CYV15G0101DXB

Single-channel HOTLink II™ Transceiver

• Compatible with

Features

— fiber-optic modules

• Single-channeltransceiverfor195to1500MBaudserial

— copper cables

— circuit board traces

• JTAG boundary scan

• Built-In Self-Test (BIST) for at-speed link testing

• Per-channel Link Quality Indicator

— Analog signal detect

— Digital signal detect

• Low power 1.25W @ 3.3V typical

• Single 3.3V supply

• 100-ball BGA

• 0.25ꢁ BiCMOS technology

signaling rate

• Second-generation HOTLink^®technology

• Compliant to multiple standards

— ESCON, DVB-ASI, Fibre Channel and Gigabit

Ethernet (IEEE802.3z)

— CYV15G0101DXB also compliant to SMPTE 259M

and SMPTE 292M

— 8B/10B encoded or 10-bit unencoded data

• Selectable parity check/generate

• Selectable input clocking options

• Selectable output clocking options

• MultiFrame™ Receive Framer

Functional Description

— Bit and Byte alignment

— Comma or full K28.5 detect

The CYP(V)15G0101DXB^[1]single-channel HOTLink II™

transceiver is a point-to-point communications building block

allowing the transfer of data over a high-speed serial link

(optical fiber, balanced, and unbalanced copper transmission

lines) at signaling speeds ranging from 195 to 1500 MBaud.

— Single- or Multi-Byte framer for byte alignment

— Low-latency option

• Synchronous LVTTL parallel input and parallel output

interface

The transmit channel accepts parallel characters in an Input

it to serial data. The receive channel accepts serial data and

converts it to parallel data, frames the data to character bound-

aries, decodes the framed characters into data and special

characters, and presents these characters to an Output

• Internal phase-locked loops (PLLs) with no external

PLL components

• Dual differential PECL-compatible serial inputs

— Internal DC-restoration

• Dual differential PECL-compatible serial outputs

— Source matched for driving 50ꢀ transmission lines

— No external bias resistors required

— Signaling-rate controlled edge-rates

• Optional Elasticity Buffer in Receive Path

• Optional Phase Align Buffer in Transmit Path

independent

host

systems

and

corresponding

CYP(V)15G0101DXB parts. As a second-generation HOTLink

device, the CYP(V)15G0101DXB extends the HOTLink II

family with enhanced levels of integration and faster data

rates, while maintaining serial-link compatibility (data,

command, and BIST) with other HOTLink devices.

Serial Link

Backplane or Cabled

Connections

Figure 1. HOTLink II System Connections

Note:

1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices.

CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements.

CYP(V)15G0101DXB refers to both devices.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-02031 Rev. *I

Revised March 16, 2004

12 3 4 5 6 7...39

中文翻译

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与CYV15G0101DXB相关器件

型号	品牌	获取价格	描述	数据表
CYV15G0101DXB-BBC	CYPRESS	获取价格	Single-channel HOTLink Transceiver
CYV15G0101DXB-BBI	CYPRESS	获取价格	Single-channel HOTLink Transceiver
CYV15G0101DXB-BBXC	CYPRESS	获取价格	Single-channel HOTLink II⑩ Transceiver
CYV15G0101DXB-BBXI	CYPRESS	获取价格	Single-channel HOTLink II⑩ Transceiver
CYV15G0101EQ	CYPRESS	获取价格	Multi-Rate Video Cable Equalizer (SOIC)
CYV15G0101EQ_07	CYPRESS	获取价格	Multi Rate Video Cable Equalizer
CYV15G0101EQ-SXC	CYPRESS	获取价格	Multi-Rate Video Cable Equalizer (SOIC)
CYV15G0102EQ	CYPRESS	获取价格	Multi-Rate Video Cable Equalizer
CYV15G0102EQ-SXC	CYPRESS	获取价格	Multi-Rate Video Cable Equalizer
CYV15G0103EQ	CYPRESS	获取价格	Prosumer Video Cable Equalizer

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