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CYS25G0101DX-ATXC

更新时间： 2024-01-01 23:18:26
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
17页 279K
描述
SONET OC-48 Transceiver

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CYS25G0101DX-ATXC 技术参数

生命周期：Active包装说明：BGA, BGA100,10X10,40
Reach Compliance Code：compliant风险等级：5.82
JESD-30 代码：S-PBGA-B100端子数量：100
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA100,10X10,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1.5,3.3 V
认证状态：Not Qualified子类别：ATM/SONET/SDH ICs
表面贴装：YES技术：BICMOS
电信集成电路类型：ATM/SONET/SDH TRANSCEIVER温度等级：COMMERCIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

CYS25G0101DX-ATXC 数据手册

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CYS25G0101DX  
SONET OC-48 Transceiver  
Features  
Functional Description  
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SONET OC-48 operation  
The CYS25G0101DX SONET OC-48 Transceiver is a commu-  
nications building block for high speed SONET data communica-  
tions. It provides complete parallel-to-serial and serial-to-parallel  
conversion, clock generation, and clock and data recovery  
operations in a single chip optimized for full SONET compliance.  
Bellcore and ITU jitter compliance  
2.488 GBaud serial signaling rate  
Multiple selectable loopback or loop through modes  
Single 155.52 MHz reference clock  
Transmit Path  
New data is accepted at the 16-bit parallel transmit interface at  
a rate of 155.52 MHz. This data is passed to a small integrated  
FIFO to allow flexible transfer of data between the SONET  
processor and the transmit serializer. As each 16-bit word is read  
from the transmit FIFO, it is serialized and sent out to the high  
speed differential line driver at a rate of 2.488 Gbits/second.  
Transmit FIFO for flexible data interface clocking  
16-bit parallel-to-serial conversion in transmit path  
Serial-to-16-bit parallel conversion in receive path  
Synchronous parallel interface  
Ë
LVPECL compliant  
HSTL compliant  
Receive Path  
Ë
As serial data is received at the differential line receiver, it is  
passed to a clock and data recovery (CDR) PLL that extracts a  
precision low jitter clock from the transitions in the data stream.  
This bit rate clock is used to sample the data stream and receive  
the data. Every 16-bit times, a new word is presented at the  
receive parallel interface along with a clock.  
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Internal transmit and receive phase-locked loops (PLLs)  
Differential CML serial input  
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50 mV input sensitivity  
100 Internal termination and DC restoration  
Ω
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Differential CML serial output  
Source matchedfor 50 transmission lines (100  
transmission lines)  
Parallel Interface  
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Ω
Ω differential  
The parallel I/O interface supports high speed bus communica-  
tions using HSTL signaling levels to minimize both power  
consumption and board landscape. The HSTL outputs are  
capable of driving unterminated transmission lines of less than  
70 mm and terminated 50Ω transmission lines of more than twice  
that length.  
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Direct interface to standard fiber optic modules  
Less than 1.0W typical power  
120-pin 14 mm × 14 mm TQFP  
The CYS25G0101DX Transceiver’s parallel HSTL I/O can also  
be configured to operate at LVPECL signaling levels. This is  
done externally by changing VDDQ, VREF and creating a simple  
circuit at the termination of the transceiver’s parallel output  
interface.  
Standby power saving mode for inactive loops  
0.25µ BiCMOS technology  
Pb-free packages available  
Cypress Semiconductor Corporation  
•
198 Champion Court  
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San Jose  
,
CA 95134-1709  
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408-943-2600  
Document Number: 38-02009 Rev. *K  
Revised July 27, 2007  
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