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CY8CPLC20-48LTXI PDF预览

CY8CPLC20-48LTXI

更新时间: 2024-01-03 22:23:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器和处理器外围集成电路uCs集成电路uPs集成电路PC通信
页数 文件大小 规格书
44页 1404K
描述
Powerline Communication Solution

CY8CPLC20-48LTXI 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC48,.27SQ,20
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.08JESD-30 代码:S-XQCC-N48
JESD-609代码:e4长度:7 mm
湿度敏感等级:3端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Microprocessor ICs
最大压摆率:14 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CY8CPLC20-48LTXI 数据手册

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CY8CPLC20  
Powerline Communication Solution  
Flexible On-Chip Memory  
32 KB Flash Program Storage 50,000 Erase or Write Cycles  
2 KB SRAM Data Storage  
EEPROM Emulation in Flash  
Programmable Pin Configurations  
25 mA Sink, 10 mA Source on all GPIO  
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive  
Modes on all GPIO  
Up to 12 Analog Inputs on GPIO  
Configurable Interrupt on all GPIO  
Features  
Powerline Communication Solution  
Integrated Powerline Modem PHY  
Frequency Shift Keying Modulation  
Configurable baud rates up to 2400 bps  
Powerline Optimized Network Protocol  
Integrates Data Link, Transport, and Network Layers  
Supports Bidirectional Half Duplex Communication  
8-bit CRC Error Detection to Minimize Data Loss  
I2C enabled Powerline Application Layer  
Supports I2C Frequencies of 50, 100, and 400 kHz  
Additional System Resources  
I2C Slave, Master, and Multi-Master to 400 kHz  
Watchdog and Sleep Timers  
Reference Designs for 110V/240V AC and 12V/24V AC/DC  
Powerlines  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
Reference Designs comply with CENELEC EN  
50065-1:2001 and FCC Part 15  
On-Chip Precision Voltage Reference  
Powerful Harvard Architecture Processor  
M8C Processor Speeds to 24 MHz  
Two 8x8 Multiply, 32-Bit Accumulate  
Programmable System Resources (PSoC® Blocks)  
12 Rail-to-Rail Analog PSoC Blocks provide:  
• Up to 14-Bit ADCs  
Complete Development Tools  
Free Development Software (PSoC Designer™)  
Full Featured In-Circuit Emulator (ICE) and Programmer  
Full Speed Emulation  
Complex Breakpoint Structure  
128 KB Trace Memory  
• Up to 9-Bit DACs  
Complex Events  
C Compilers, Assembler, and Linker  
• Programmable Gain Amplifiers  
• Programmable Filters and Comparators  
16 Digital PSoC Blocks provide:  
• 8 to 32-Bit Timers, Counters, and PWMs  
• CRC and PRS Modules  
• Up to Four Full Duplex UARTs  
• Multiple SPITM Masters or Slaves  
• Connectable to all GPIO Pins  
Complex Peripherals by Combining Blocks  
Logic Block Diagram  
Powerline Communication Solution  
Embedded Application  
Powerline Network  
Programmable  
Protocol  
System Resources  
Digital and Analog  
Peripherals  
Additional System  
Physical Layer FSK  
Modem  
Resources  
MAC, Decimator, I2C,  
SPI, UART etc.  
PLC Core  
PSoC Core  
Powerline Transceiver Packet  
AC/DC Powerline Coupling Circuit  
(110V/240V AC, 12V/24V AC/DC etc.)  
Powerline  
Cypress Semiconductor Corporation  
Document Number: 001-48325 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 05, 2009  
[+] Feedback  

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