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CY8CLED03G01-56LTXI PDF预览

CY8CLED03G01-56LTXI

更新时间: 2024-02-07 00:44:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 显示驱动器驱动程序和接口接口集成电路
页数 文件大小 规格书
52页 1388K
描述
PowerPSoC Intelligent LED Driver

CY8CLED03G01-56LTXI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:8 X 8 MM, LEAD FREE, MO-220, QFN-56
针数:56Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:8.59Is Samacsys:N
数据输入模式:SERIAL接口集成电路类型:LED DISPLAY DRIVER
JESD-30 代码:S-XQCC-N56JESD-609代码:e3
长度:8 mm湿度敏感等级:3
复用显示功能:NO功能数量:1
区段数:3端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC56,.31SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:5,7/32 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Display Drivers
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:8 mm
最小 fmax:8 MHzBase Number Matches:1

CY8CLED03G01-56LTXI 数据手册

 浏览型号CY8CLED03G01-56LTXI的Datasheet PDF文件第2页浏览型号CY8CLED03G01-56LTXI的Datasheet PDF文件第3页浏览型号CY8CLED03G01-56LTXI的Datasheet PDF文件第4页浏览型号CY8CLED03G01-56LTXI的Datasheet PDF文件第5页浏览型号CY8CLED03G01-56LTXI的Datasheet PDF文件第6页浏览型号CY8CLED03G01-56LTXI的Datasheet PDF文件第7页 
CY8CLED04D01, CY8CLED04D02  
CY8CLED04G01, CY8CLED03D01  
CY8CLED03D02, CY8CLED03G01  
CY8CLED02D01, CY8CLED01D01  
PowerPSoC® Intelligent LED Driver  
1. Features  
Integrated Power Peripherals  
Four internal 32V low side N-Channel power  
FETs  
6 to 12-bit incremental ADCs  
LED based express drivers  
Binning compensation  
Temperature feedback  
Up to 9-bit DACs  
Programmable gain amplifiers  
Programmable filters and comparators  
8 to 32-bit timers and counters  
Complex peripherals by combining blocks  
Configurable to all GPIO pins  
• R  
– 0.5Ω for 1.0A devices  
DS(ON)  
Applications  
Stage LED lighting  
• Up to 2 MHz configurable switching frequency  
Four hysteretic controllers  
Architectural LED lighting  
General purpose LED lighting  
Automotive and emergency vehicle LED lighting  
Landscape LED lighting  
Display LED lighting  
Effects LED lighting  
Signage LED lighting  
• Independently programmable upper and  
lower thresholds  
• Programmable minimum on/off timers  
Four low side gate drivers with programmable  
drive strength  
Programmable Pin Configurations  
25 mA sink on all GPIO and function pins  
Pull up, pull down, high Z, strong, or open drain  
drive modes on all GPIO and function pins  
Up to 10 analog inputs on GPIO  
Two 30 mA analog outputs on GPIO  
Configurable interrupt on all GPIO  
Four precision high side current sense amplifiers  
Three 16-bit LED dimming modulators: PrISM,  
DMM, and PWM  
Device Options  
CY8CLED04D0x  
• Four internal FETs with 0.5A and 1.0A options  
• Four external gate drivers  
CY8CLED04G01  
• Four external gate drivers  
CY8CLED03D0x  
• Three internal FETs with 0.5A and 1.0A  
options  
• Three external gate drivers  
CY8CLED03G01  
• Three external gate drivers  
CY8CLED02D01  
• Two 1.0A internal FETs  
• Two external gate drivers  
CY8CLED01D01  
• One 1.0A internal FET  
• One external gate driver  
Six fast response (100 ns) voltage comparators  
Six 8-bit reference DACs  
Flexible On-chip Memory  
16K Flash program storage 50,000 erase and  
write cycles  
Built-in switching regulator eliminates external  
5V supply  
1K SRAM data storage  
Multiple topologies including floating load buck,  
floating load buck-boost, and boost  
In-System Serial Programming (ISSP)  
Partial Flash updates  
M8C CPU Core  
Flexible protection modes  
EEPROM emulation in Flash  
Processor speeds up to 24 MHz  
®
Advanced Peripherals (PSoC Blocks)  
Complete Development Tools  
Free development software: PSoC Designer  
5.0™  
Full featured, In-Circuit Emulator and Program-  
mer  
Full speed emulation  
Complex breakpoint structure  
128 kBytes trace memory  
Capacitive sensing application capability  
DMX512 interface  
DALI interface  
I2C master or slave  
Full-duplex UARTs  
Multiple SPI masters or slaves  
Integrated temperature sensor  
Up to 12-bit ADCs  
Visual Embedded Design  
56-pin QFN Package  
Figure 1-1. PowerPSoC Architectural Block Diagram  
Analog  
Drivers  
Port 2  
Port 1  
Port 0  
FN0  
CSA  
CSA  
SYSTEM BUS  
Analog Mux Bus  
PWM Controller  
Channels(LV)  
Gate  
Power  
Global Digital Interconnect  
Logic Core  
Driver(LV) FETs (HV)  
Global Analog Interconnect  
PrISM/ DMM/  
PWM  
PSoC CORE  
Clock Signals  
SRAM  
(1 K bytes)  
Hysteretic  
DAC  
Flash Nonvolatile  
Memory(1 6 K )  
Supervisory ROM  
( SROM)  
Decoder  
GDRV  
PWM  
Analog Block  
CPU  
Core  
(M 8C)  
Sleep and  
Watchdog  
Interrupt  
Controller  
C1  
System Bus  
C2  
C3  
C4  
C5  
Hysteretic  
DAC  
PWM  
GDRV  
GDRV  
24 MHz Internal Main  
Oscillator(IMO)  
Internal Low Speed  
Oscillator( ILO)  
Multiple Clock Sources  
C6  
ANALOG SYSTEM  
Hysteretic  
PWM  
DIGITAL SYSTEM  
Digital PSoC Block Array  
DBB00 DBB 01 DCB 02 DCB 03  
Comparator  
Bank  
DAC  
DAC  
Analog PSoC  
Block Array  
Analog  
Ref  
DAC  
DAC  
CT  
SC  
CT  
SC  
DBB01 DBB 11 DCB 12 DCB13  
AINX  
Hysteretic  
PWM  
2
Digital Rows  
SC  
SC  
GDRV  
DAC  
2Analog Columns  
DAC Bank  
Vref  
POR and LVD  
Internal  
Voltage  
System Resets Reference  
Digital  
Clocks  
MACs  
(2)  
Decimator  
Type2)  
IO Analog  
Multiplexer  
POWER PERIPHERALS  
I2C  
SW Regulator  
(
PSoC SYSTEM RESOURCES  
CSA  
CSA  
Cypress Semiconductor Corporation  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Document Number: 001-46319 Rev. *G  
Revised July 20, 2009  
[+] Feedback  

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