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CY8C9540A-24PVXI PDF预览

CY8C9540A-24PVXI

更新时间: 2024-01-28 02:47:02
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 并行IO端口微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 721K
描述
20-, 40-, and 60-Bit IO Expander with EEPROM

CY8C9540A-24PVXI 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:SSOP包装说明:SSOP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.76Samacsys Confidence:3
Samacsys Status:Released2D Presentation:https://componentsearchengine.com/2D/0T/985093.1.1.png
Schematic Symbol:https://componentsearchengine.com/symbol.php?partID=985093PCB Footprint:https://componentsearchengine.com/footprint.php?partID=985093
3D View:https://componentsearchengine.com/viewer/3D.php?partID=985093Samacsys PartID:985093
Samacsys Image:https://componentsearchengine.com/Images/9/CY8C9540A-24PVXIT.jpgSamacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/CY8C9540A-24PVXIT.jpg
Samacsys Pin Count:48Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:48-pin SSOP (300mils)_inches
Samacsys Released Date:2020-06-05 04:19:38Is Samacsys:N
其他特性:IT ALSO OPERATES AT 5 VJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:15.875 mm
湿度敏感等级:3位数:40
I/O 线路数量:40端口数量:8
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3/5 V
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Parallel IO Port最大供电电压:5.25 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

CY8C9540A-24PVXI 数据手册

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CY8C9520A, CY8C9540A  
CY8C9560A  
20-, 40-, and 60-Bit IO Expander with  
EEPROM  
Features  
Overview  
I2C™ interface logic electrically compatible with SMBus  
The CY8C95xxA is a multi-port IO expander with on board user  
available EEPROM and several PWM outputs. All devices in this  
family operate identically but differ in IO pins, number of PWMs,  
Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)  
IO data pins independently configurable as inputs, outputs,  
bi-directional input/outputs, or PWM outputs  
and internal EEPROM size.  
The CY8C95xxA operates as two I2C slave devices. The first  
device is a multi port IO expander (single I2C address to access  
all ports through registers). The second device is a serial  
EEPROM. Dedicated configuration registers can be used to  
disable the EEPROM. The EEPROM uses 2-byte addressing to  
support the 28 Kbyte EEPROM address space. The selected  
device is defined by the most significant bits of the I2C address  
or by specific register addressing.  
4/8/16 PWM sources with 8-bit resolution  
Extendable Soft Addressing™ algorithm allowing flexible  
I2C-address configuration  
Internal 3-/11-/27-Kbyte EEPROM  
User default storage, IO port settings in internal EEPROM  
Optional EEPROM Write Disable (WD) input  
The IO expander's data pins can be independently assigned as  
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.  
The individual data pins can be configured as open drain or  
collector, strong drive (10 mA source, 25 mA sink), resistively  
pulled up or down, or high impedance. The factory default config-  
uration is pulled up internally.  
Interrupt output indicates input pin level changes and Pulse  
Width Modulator (PWM) state changes  
Internal Power On Reset (POR)  
Internal configurable Watchdog timer  
The system master writes to the IO configuration registers  
through the I2C bus. Configuration and output register settings  
are storable as user defaults in a dedicated section of the  
EEPROM. If user defaults were stored in EEPROM, they are  
restored to the ports at power up. While this device can share the  
bus with SMBus devices, it can only communicate with I2C  
masters.  
Top Level Block Diagram  
WD  
EEPROM  
User  
Settings  
Area  
User  
Available  
Area  
There is one dedicated pin that is configured as an interrupt  
output (INT) and can be connected to the interrupt logic of the  
system master. This signal can inform the system master that  
there is incoming data on its ports or that the PWM output state  
was changed.  
Clocks  
32 kHz  
24 MHz  
GPort 0  
GPort 1  
GPort 2  
GPort 3  
8 Bit IO  
5 Bit IO  
The EEPROM is byte readable and supports byte-by-byte  
writing. A pin can be configured as an EEPROM Write Disable  
(WD) input that blocks write operations when set high. The  
configuration registers can also disable EEPROM operations.  
1.5 MHz  
3 Bit IO  
or A4-A6  
93.75 kHz  
4 Bit IO  
or A1-A3, WD6  
The CY8C95xxA has one fixed address pin (A0) and up to six  
additional pins (A1-A6), which allow up to 128 devices to share  
a common two wire I2C data bus. The Extendable Soft  
Addressing algorithm provides the option to choose the number  
of pins needed to assign the desired address. Pins not used for  
address bits are available as GPIO pins.  
Divider (1-255)  
Control  
Unit  
PWM 0  
8 Bit IO  
8 Bit IO  
PWM 15  
GPort 7  
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)  
independently configurable 8-bit PWMs. These PWMs are listed  
as PWM0-PWM15. Each PWM can be clocked by one of six  
available clock sources.  
SCL  
SDA  
INT  
A0  
Vdd  
Vss  
Power-on-Reset  
For details on how to configure I2C, see Application Note  
"Communication - I2C Port Expander with Flash Storage -  
AN2304" at http://www.cypress.com/design/2304.  
Cypress Semiconductor Corporation  
Document Number: 38-12036 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 03, 2007  
[+] Feedback  

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