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CY8C5568AXI-060T PDF预览

CY8C5568AXI-060T

更新时间: 2024-01-14 05:02:24
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器时钟
页数 文件大小 规格书
112页 4126K
描述
Micro Peripheral IC

CY8C5568AXI-060T 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.8
Base Number Matches:1

CY8C5568AXI-060T 数据手册

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PRELIMINARY  
PSoC® 5: CY8C55 Family Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
With its unique array of configurable blocks, PSoC® 5 is a true system-level solution providing microcontroller unit (MCU), memory,  
analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal  
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples  
(near DC voltages) to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on  
every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including  
interfaces such as USB, multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C55  
family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3  
microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean  
primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities  
for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware  
updates.  
Library of advanced peripherals  
Features  
• Cyclic redundancy check (CRC)  
32-bit ARM Cortex-M3 CPU core  
• Pseudo random sequence (PRS) generator  
DC to 67 MHz operation  
• Local interconnect network (LIN) bus 2.0  
• Quadrature decoder  
2F0la-syheaprroregtreanmtiomne, manodrym, uupltitpole25s6ecKuBri,ty10fe0a,0tu0r0eswrite cycles,  
Analog peripherals (1.71 V VDDA 5.5 V)  
Up to 64 KB SRAM memory  
1.024 V ±1% internal voltage reference across –40 °C to  
(2E-KEBPRelOecMtr)icmaellymeorrays, a1bmleillpiorongcryacmlemsa, abnledr2e0ady-eoanrlsyrmeteemntoioryn  
+85 °C (128 ppm/°C)  
Configurable delta-sigma ADC with 8- to 20-bit resolution  
• Sample rates up to 192 ksps  
A24M-cBhAanhnigehl-dpiererfcotrmmeamncoerybuascc(eAsHsB()DbMuAs)awccitehsms ultilayer  
• Programmable chained descriptors and priorities  
• High bandwidth 32-bit transfer support  
• Programmable gain stage: ×0.25 to ×16  
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion  
ratio (SINAD), ±1-bit INL/DNL  
Low voltage, ultra low power  
Operating voltage range:1.8 V to 5.5 V  
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL  
Two SAR ADCs, each 12-bit at 1 Msps[2]  
oHuigtphu-et fficiency boost regulator from 1.8 V input to 5.0 V  
Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs  
Four comparators with 95-ns response time  
2 mA at 6 MHz  
Four uncommitted opamps with 25-mA drive capability  
Low power modes including:  
cFoonufrigcuornaftiigounrsabalreempruoltgifruanmcmtioanblaengaaloing abmlopclkifsie. rE(xPaGmAp)le,  
transimpedance amplifier (TIA), mixer, and Sample and Hold  
CapSense support  
• 2-µA sleep mode with real time clock (RTC) and  
low-voltage detect (LVD) interrupt  
• 300-nA hibernate mode with RAM retention  
Versatile I/O system  
Programming, debug, and trace  
vJiTeAwGer(4(SwWirVe)),,saenrdiaTl wRiAreCdEePbOuRgT(SinWteDr)fa(c2ewsire), single wire  
Cortex-M3 flash patch and breakpoint (FPB) block  
gCeonrteerxa-tMes3aEnminbsetdrudcetdioTnrtarcaeceMsatrceroacme.ll™ (ETM™)  
28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs)  
Any GPIO to any digital or analog peripheral routability  
LCD direct drive from any GPIO, up to 46×16 segments  
CapSense® support from any GPIO[1]  
1.2 V to 5.5 V I/O interface voltages, up to 4 domains  
Maskable, independent IRQ on any pin or port  
Schmitt-trigger transistor-transistor logic (TTL) inputs  
tCraocrteexin-Mfo3rmdaattiaonwatchpoint and trace (DWT) generates data  
uCsoerdtefxo-rMp3riInntsf-tsrutymleednetabtuiogngiTnrgace Macrocell (ITM) can be  
aDnWdTt,raEcTeMs,yasntedmITsMvbialotchkesScWomVmournTicRaAteCwEiPthOoRffT-chipdebug  
pAullllG-uPpI/Opusllc-odnofwignu,rHabigleh-aZs, oorpestnrodnrgainouhtpiguht/low,  
25 mA sink on SIO  
Digital peripherals  
Bootloader programming supportable through I2C, SPI,  
UART, USB, and other interfaces  
Precision, programmable clocking  
d2i0gittoal2b4lopcrkosgr(aUmDmBsa)ble logic device (PLD) based universal  
Full CAN 2.0b 16 RX, 8 TX buffers[2]  
v3otlota6g2eMraHnzgeinternal oscillator over full temperature and  
4- to 25 MHz crystal oscillator for crystal PPM accuracy  
Internal PLL clock generation up to 67 MHz  
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator  
Four 16-bit configurable timers, counters, and PWM blocks  
i6m7pMleHmze,n2t4fi-nbiittefiixmepduplsoeinrtedsipgoitnaslefil(tFerIRb)loacnkd(iDnfFinBit)etoimpulse  
response (IIR) filters  
32.768 KHz watch crystal oscillator  
Low power internal oscillator at 1, 33, and 100 kHz  
Library of standard peripherals  
Temperature and packaging  
–40 °C to +85 °C industrial temperature  
68-pin QFN and 100-pin TQFP package options.  
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs  
• SPI, UART, and I2C  
• Many others available in catalog  
Notes  
1. GPIOs with opamp outputs are not recommended for use with CapSense.  
2. This feature on select devices only. See Ordering Information on page 105 for details.  
Cypress Semiconductor Corporation  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Document Number: 001-66235 Rev. **  
Revised March 28, 2011  
[+] Feedback  

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