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5962-9459906MXX PDF预览

5962-9459906MXX

更新时间: 2023-03-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
15页 491K
描述
Non-Volatile SRAM, 8KX8, 35ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

5962-9459906MXX 数据手册

 浏览型号5962-9459906MXX的Datasheet PDF文件第2页浏览型号5962-9459906MXX的Datasheet PDF文件第3页浏览型号5962-9459906MXX的Datasheet PDF文件第4页浏览型号5962-9459906MXX的Datasheet PDF文件第5页浏览型号5962-9459906MXX的Datasheet PDF文件第6页浏览型号5962-9459906MXX的Datasheet PDF文件第7页 
STK12C68  
STK12C68-M SMD#5962-94599  
8K x 8 AutoStore™ nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
• 25ns, 45ns and 55ns Access Times  
The Simtek STK12C68 is a fast static RAM with a  
• “Hands-off” Automatic STORE with External  
68μF Capacitor on Power Down  
STORE to Nonvolatile Elements Initiated by  
Hardware, Software or AutoStore™ on Power  
Down  
nonvolatile element incorporated in each static  
memory cell. The SRAM can be read and written an  
unlimited number of times, while independent, non-  
volatile data resides in Nonvolatile Elements. Data  
transfers from the SRAM to the Nonvolatile Elements  
(the STORE operation) can take place automatically  
on power down. A 68μF or larger capacitor tied from  
VCAP to ground guarantees the STORE operation,  
regardless of power-down slew rate or loss of power  
from “hot swapping”. Transfers from the Nonvolatile  
Elements to the SRAM (the RECALL operation) take  
place automatically on restoration of power. Initia-  
tion of STORE and RECALL cycles can also be soft-  
ware controlled by entering specific read  
sequences. A hardware STORE may be initiated with  
the HSB pin.  
RECALL to SRAM Initiated by Software or  
Power Restore  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments (Commercial/Industrial)  
• 100-Year Data Retention in Nonvolatile Ele-  
ments (Commercial/Industrial)  
• Commercial, Industrial and Military Tempera-  
tures  
• 28-Pin SOIC, DIP and LCC Packages  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
VCCX  
VCAP  
1
V
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CCX  
W
HSB  
CAP  
2
A
12  
3
A
7
4
POWER  
CONTROL  
A
A
6
8
QUANTUM TRAP  
128 x 512  
5
A
A
9
A
11  
5
6
A
4
7
A
G
A
3
2
8
A5  
A6  
A
10  
9
A
E
1
STORE  
10  
11  
12  
13  
14  
A
DQ  
0
7
STORE/  
RECALL  
CONTROL  
DQ  
DQ  
DQ  
V
DQ  
6
DQ  
5
DQ  
4
0
HSB  
A7  
1
STATIC RAM  
ARRAY  
2
RECALL  
DQ  
A8  
SS  
3
128 x 512  
A9  
28 - LCC  
28 - DIP  
28 - SOIC  
A11  
A12  
SOFTWARE  
DETECT  
A0 - A12  
PIN NAMES  
DQ0  
DQ1  
DQ2  
COLUMN I/O  
A - A  
Address Inputs  
0
12  
COLUMN DEC  
DQ -DQ  
0
Data In/Out  
7
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
E
Chip Enable  
Write Enable  
Output Enable  
W
A0 A1 A2 A3 A4 A10  
G
G
HSB  
Hardware Store Busy (I/O)  
Power (+ 5V)  
Capacitor  
E
V
V
V
CCX  
CAP  
SS  
W
Ground  
March 2006  
1
Document Control # ML0008 rev 0.5  

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