Datasheet > 5962-9452201MXX

5962-9452201MXX

更新时间： 2024-01-24 17:34:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动逻辑集成电路
页数	文件大小	规格书
14页	326K
描述
PLL Based Clock Driver, 7B Series, 2 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32

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5962-9452201MXX 技术参数

生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	QCCN,	针数：	32
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	系列：	7B
输入调节：	STANDARD	JESD-30 代码：	R-CQCC-N32
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	4
反相输出次数：		端子数量：	32
实输出次数：	2	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	传播延迟（tpd）：	0.7 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	1.5 ns
筛选级别：	MIL-STD-883	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	NO LEAD
端子位置：	QUAD	最小 fmax：	80 MHz

5962-9452201MXX 数据手册

CY7B991

CY7B992

Programmable Skew Clock Buffer

functions. These multiple-output clock drivers provide the sys-

tem integrator with functions necessary to optimize the timing

of high-performance computer systems. Eight individual driv-

ers, arranged as four pairs of user-controllable outputs, can

each drive terminated transmission lines with impedances as

low as 50Ω while delivering minimal and specified output skews

and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Features

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 80-MHz output operation

• User-selectable output functions

— Selectable skew to 18 ns

— Inverted and non-inverted

Each output can be hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs able to skew up

to ±6 time units from their nominal “zero” skew position. The com-

pletely integrated PLL allows external load and transmission line

delay effects to be canceled. When this “zero delay” capability of the

PSCB is combined with the selectable output skew functions, the

user can create output-to-output delays of up to ±12 time units.

— Operation at

and

input frequency

⁄

— Operation at 2x and 4x input frequency (input as low

as 3.75 MHz)

• Zero input to output delay

• 50% duty-cycle outputs

Outputs drive 50 terminated lines

•

Ω

• Low operating current

• 32-pin PLCC/LCC package

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Compatible with a Pentium™-based processor

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low-frequency clock that can be multi-

plied by two or four at the clock destination. This facility mini-

mizes clock distribution difficulty while allowing maximum sys-

tem clock speed and flexibility.

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buff-

ers (PSCB) offer user-selectable control over system clock

Logic Block Diagram

Pin Configuration

TEST

PLCC/LCC

PHASE

FREQ

DET

VCO AND

TIME UNIT

GENERATOR

FILTER

REF

32 31 30

2F0

GND

1F1

1F0

3F1

4F0

4Q0

4Q1

4F0

4F1

SELECT

INPUTS

(THREE

LEVEL)

CCQ

CY7B991

CY7B992

CCN

SKEW

SELECT

MATRIX

CCN

3Q0

3Q1

3F0

3F1

4Q1

1Q0

1Q1

GND

4Q0

GND

2Q0

2Q1

2F0

2F1

14 15 16 17 18 19 20

1Q0

1Q1

1F0

1F1

7B991–2

7B991–1

Pentium is a trademark of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

November 1991 - Revised July 7, 1997

12 3 4 5 6 7...14

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