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5962-9061102XA PDF预览

5962-9061102XA

更新时间: 2024-01-25 08:27:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟输入元件可编程逻辑
页数 文件大小 规格书
6页 84K
描述
UV PLD, 40ns, PAL-Type, CMOS, CDIP28, 0.300 INCH, WINDOWED, CERDIP-28

5962-9061102XA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred包装说明:WDIP,
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.32
其他特性:MACROCELLS INTERCONNECTED BY PIA; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK最大时钟频率:27 MHz
JESD-30 代码:R-GDIP-T28JESD-609代码:e0
长度:37.0205 mm专用输入次数:7
I/O 线路数量:16端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
组织:7 DEDICATED INPUTS, 16 I/O输出函数:MACROCELL
封装主体材料:CERAMIC, GLASS-SEALED封装代码:WDIP
封装形状:RECTANGULAR封装形式:IN-LINE, WINDOW
峰值回流温度(摄氏度):NOT SPECIFIED可编程逻辑类型:UV PLD
传播延迟:40 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

5962-9061102XA 数据手册

 浏览型号5962-9061102XA的Datasheet PDF文件第2页浏览型号5962-9061102XA的Datasheet PDF文件第3页浏览型号5962-9061102XA的Datasheet PDF文件第4页浏览型号5962-9061102XA的Datasheet PDF文件第5页浏览型号5962-9061102XA的Datasheet PDF文件第6页 
EPLD  
CY7C340 EPLD Family  
Multiple Array Matrix High-Density EPLDs  
CY7C342B. This allows the designer to replace 50 or more  
TTL packages with just one MAX EPLD. The family comes in  
a range of densities, shown below. By standardizing on a few  
MAX building blocks, the designer can replace hundreds of  
different 7400 series part numbers currently used in most dig-  
ital systems.  
Features  
• Erasable, user-configurable CMOS EPLDs capable of  
implementing high-density custom logic functions  
• 0.8-micron double-metal CMOS EPROM technology  
(CY7C34X)  
The family is based on an architecture of flexible macrocells  
grouped together into Logic Array Blocks (LABs). Within the  
LAB is a group of additional product terms called expander  
product terms. These expanders are used and shared by the  
macrocells, allowing complex functions of up to 35 product  
terms to be easily implemented in a single macrocell. A Pro-  
grammable Interconnect Array (PIA) globally routes all signals  
within devices containing more than one LAB. This architec-  
ture is fabricated on the Cypress 0.8-micron, double-lay-  
er-metal CMOS EPROM process, yielding devices with signif-  
icantly higher integration, density and system clock speed than  
the largest of previous generation EPLDs. The CY7C34XB de-  
vices are 0.65-micron shrinks of the original 0.8-micron family.  
The CY7C34XBs offer faster speed bins for each device in the  
Cypress MAX family.  
• Advanced 0.65-micron CMOS technology to increase  
performance (CY7C34XB)  
• Multiple Array MatriX architecture optimized for speed,  
density, and straightforward design implementation  
— Programmable Interconnect Array (PIA) simplifies  
routing  
— Flexible macrocells increase utilization  
— Programmable clock control  
— Expander product terms implement complex logic  
functions  
General Description  
The Cypress Multiple Array Matrix (MAX®) family of EPLDs  
provides a user-configurable, high-density solution to gener-  
al-purpose logic integration requirements. With the combina-  
tion of innovative architecture and state-of-the-art process, the  
MAX EPLDs offer LSI density without sacrificing speed.  
The density and performance of the CY7C340 family is ac-  
cessed using Cypress’s Warp™, Warp Professional™, or  
Warp Enterprise™ design software. Warp provides  
state-of-the-art synthesis, fitting, simulation and other devel-  
opment tools at a very low cost. Warp Professional or Warp  
Enterprise are sophisticated CAE tool that include behavior-  
al simulation, graphical waveform editing and more. Consult  
the datasheets for Warp, Warp Professional and Warp Enter-  
prise™ for more information about these development tools.  
The MAX architecture makes it ideal for replacing large  
amounts of TTL SSI and MSI logic. For example, a 74161  
counter utilizes only 3% of the 128 macrocells available in the  
CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes  
less than 1% of the over 1,000 product terms in the  
Max Family Members  
Feature  
Macrocells  
CY7C344(B)  
CY7C343(B)  
CY7C342B  
128  
CY7C346(B)  
CY7C341B  
192  
32  
64  
64  
128  
MAX Flip-Flops  
32  
128  
128  
192  
[1]  
MAX Latches  
64  
23  
128  
35  
256  
256  
384  
[2]  
MAX Inputs  
59  
84  
64  
71  
MAX Outputs  
Packages  
16  
28  
52  
64  
28H,J,W,P  
44H,J  
68H,J,R  
84H,J 100R,N  
84H,J,R  
Key: P—Plastic DIP; H—Windowed Ceramic Leaded Chip Carrier; J—Plastic J-Lead Chip Carrier; R—Windowed Pin Grid Array;  
W—Windowed Ceramic DIP; N—Plastic Quad Flat Pack  
Notes:  
1. When all expander product terms are used to implement latches.  
2. With one output.  
PAL is a registered trademark of Advanced Micro Devices.  
MAX is a registered trademark of Altera Corporation.  
FLASH370, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
July 19, 2000  

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