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5962-8952306EA PDF预览

5962-8952306EA

更新时间： 2024-02-03 13:49:26
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
13页 269K
描述
FIFO, 64X4, 40ns, Asynchronous, CMOS, CDIP16, 0.300 INCH, CERDIP-16

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5962-8952306EA 技术参数

生命周期：Transferred包装说明：DIP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.52
Is Samacsys：N最长访问时间：40 ns
周期时间：66.67 nsJESD-30 代码：R-GDIP-T16
JESD-609代码：e0长度：19.431 mm
内存密度：256 bit内存宽度：4
功能数量：1端子数量：16
字数：64 words字数代码：64
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：64X4
可输出：NO封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

5962-8952306EA 数据手册

 浏览型号5962-8952306EA的Datasheet PDF文件第2页浏览型号5962-8952306EA的Datasheet PDF文件第3页浏览型号5962-8952306EA的Datasheet PDF文件第4页浏览型号5962-8952306EA的Datasheet PDF文件第5页浏览型号5962-8952306EA的Datasheet PDF文件第6页浏览型号5962-8952306EA的Datasheet PDF文件第7页 
1CY7C402  
CY7C401/CY7C403  
CY7C402/CY7C404  
64 x 4 Cascadable FIFO  
64 x 5 Cascadable FIFO  
words. Both the CY7C403 and CY7C404 have an output en-  
able (OE) function.  
Features  
• 64 x 4 (CY7C401 and CY7C403)  
64 x 5 (CY7C402 and CY7C404)  
The devices accept 4- or 5-bit words at the data input (DI –  
0
DI ) under the control of the shift in (SI) input. The stored  
n
High-speed first-in first-out memory (FIFO)  
words stack up at the output (DO – DO ) in the order they  
0
n
• Processed with high-speed CMOS for optimum  
speed/power  
• 25-MHz data rates  
• 50-ns bubble-through time—25 MHz  
• Expandable in word width and/or length  
• 5-volt power supply ± 10% tolerance, both commercial  
and military  
• Independent asynchronous inputs and outputs  
• TTL-compatible interface  
• Output enable function available on CY7C403 and  
CY7C404  
were entered. A read command on the shift out (SO) input  
causes the next to last word to move to the output and all data  
shifts down once in the stack. The input ready (IR) signal acts  
as a flag to indicate when the input is ready to accept new data  
(HIGH), to indicate when the FIFO is full (LOW), and to provide  
a signal for a cascading. The output ready (OR) signal is a flag  
to indicate the output contains valid data (HIGH), to indicate  
the FIFO is empty (LOW), and to provide a signal for cascad-  
ing.  
Parallel expansion for wider words is accomplished by logical-  
ly ANDing the IR and OR signals to form composite signals.  
Serial expansion is accomplished by tying the data inputs of  
one device to the data outputs of the previous device. The IR  
pin of the receiving device is connected to the SO pin of the  
sending device, and the OR pin of the sending device is con-  
nected to the SI pin of the receiving device.  
• Capable of withstanding greater than 2001V electro-  
static discharge  
• Pin compatible with MMI 67401A/67402A  
Functional Description  
Reading and writing operations are completely asynchronous,  
allowing the FIFO to be used as a buffer between two digital  
machines of widely differing operating frequencies. The  
25-MHz operation makes these FIFOs ideal for high-speed  
communication and controller applications.  
The CY7C401 and CY7C403 are asynchronous first-in  
first-out (FIFOs) organized as 64 four-bit words. The CY7C402  
and CY7C404 are similar FIFOs organized as 64 five-bit  
Logic Block Diagram  
Pin Configurations  
DIP  
DIP  
(CY7C401) NC  
(CY7C403) OE  
IR  
(CY7C402) NC  
(CY7C404) OE  
IR  
SI  
V
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
CC  
INPUT  
SO  
OR  
DO  
DO  
SO  
OR  
DO  
DO  
DO  
DO  
DO  
MR  
CONTROL  
WRITE POINTER  
SI  
SI  
LOGIC  
IR  
CY7C402  
CY7C404  
CY7C401  
DI  
DI  
13  
CY7C403  
12  
0
0
OUTPUT  
0
1
0
1
OE  
DO  
WRITE MULTIPLEXER  
ENABLE  
DI  
1
DI  
1
DI  
DI  
11 DO  
2
2
2
3
2
3
4
DI  
DI  
DI  
DI  
0
1
2
3
10  
9
DI  
3
GND  
DI  
3
DI  
4
GND  
DO  
MR  
0
DATAIN  
C401–2  
MEMORY  
ARRAY  
DO  
1
C401–4  
DO  
2
DATAIN  
LCC  
LCC  
(DI  
)
4
DO  
3
(DO )  
4
READ MULTIPLEXER  
READ POINTER  
MASTER  
RESET  
3 2 1 2019  
18  
3 2 1 2019  
18  
MR  
OR  
DO  
DO  
DO  
NC  
4
4
SI  
SI  
0
1
SO  
OR  
5
17 OR  
16 DO  
15 DO  
5
6
7
8
17  
16  
15  
14  
0
1
2
DI  
DI  
DI  
DI  
DI  
DI  
DI  
OUTPUT  
CONTROL  
LOGIC  
0
1
2
CY7C401  
CY7C403  
CY7C402  
CY7C404  
6
7
8
0
1
2
2
3
NC  
14  
DO  
DO  
3
910111213  
910111213  
C401–1  
C401–3  
C401–5  
Selection Guide  
7C401/2–5  
7C40X–10  
7C40X–15  
7C40X–25  
Operating Frequency (MHz)  
5
10  
75  
90  
15  
75  
90  
25  
75  
90  
Maximum Operating  
Current (mA)  
Commercial  
Military  
75  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
March 1986 – Revised April 1995  
•
408-943-2600  
1234567...13

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