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5962-8851805LX PDF预览

5962-8851805LX

更新时间: 2024-02-05 07:05:56
品牌 Logo 应用领域
赛普拉斯 - CYPRESS OTP只读存储器内存集成电路
页数 文件大小 规格书
9页 185K
描述
OTP ROM, 512X8, CMOS, CDIP24, 0.300 INCH, SLIM, HERMETIC SEALED, CERDIP-24

5962-8851805LX 技术参数

生命周期:ActiveReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.37JESD-30 代码:R-GDIP-T24
内存密度:4096 bit内存集成电路类型:OTP ROM
内存宽度:8功能数量:1
端子数量:24字数:512 words
字数代码:512工作模式:SYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:512X8封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
认证状态:Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子位置:DUALBase Number Matches:1

5962-8851805LX 数据手册

 浏览型号5962-8851805LX的Datasheet PDF文件第2页浏览型号5962-8851805LX的Datasheet PDF文件第3页浏览型号5962-8851805LX的Datasheet PDF文件第4页浏览型号5962-8851805LX的Datasheet PDF文件第5页浏览型号5962-8851805LX的Datasheet PDF文件第6页浏览型号5962-8851805LX的Datasheet PDF文件第7页 
1CY7C225A  
CY7C225A  
512 x 8 Registered PROM  
• Capable of withstanding greater than 2001V static  
discharge  
Features  
• CMOS for optimum speed/power  
• High speed  
Functional Description  
The CY7C225A is a high-performance 512-word by 8-bit  
electrically programmable read only memory packaged in a  
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip  
carrier, and 28-pin PLCC. The memory cells utilize proven  
EPROM floating gate technology and byte-wide intelligent  
programming algorithms.  
— 25 ns address set-up  
— 12 ns clock to output  
• Low power  
— 495 mW (Commercial)  
— 660 mW (Military)  
The CY7C225A replaces bipolar devices and offers the advan-  
tages of lower power, superior performance, and high  
programming yield. The EPROM cell requires only 12.5V for  
the supervoltage and low current requirements allow for gang  
programming. The EPROM cells allow for each memory  
location to be tested 100%, as each location is written into,  
erased, and repeatedly exercised prior to encapsulation. Each  
PROM is also tested for AC performance to guarantee that  
after customer programming the product will meet AC specifi-  
cation limits.  
• Synchronous and asynchronous output enables  
• On-chip edge-triggered registers  
• Buffered common PRESET and CLEAR inputs  
• EPROM technology, 100% programmable  
• Slim300-mil, 24-pinplasticor hermeticDIP, 28-pinLCC,  
or 28-pin PLCC  
5V ±10% VCC, commercial and military  
• TTL-compatible I/O  
• Direct replacement for bipolar PROMs  
Logic Block Diagram  
Pin Configurations  
DIP  
Top View  
O
O
7
A
0
1
24  
A
V
CC  
7
A
1
2
3
4
5
6
A
23  
22  
21  
6
A
8
6
ROW  
A
5
PS  
PROGRAMMABLE  
ARRAY  
A
2
ADDRESS  
MULTIPLEXER  
A
4
E
O
O
5
A
3
A
20  
19  
18  
17  
16  
CLR  
3
8-BIT  
EDGE-  
TRIGGERED  
REGISTER  
E
S
A
2
A
4
4
A
1
7
CP  
ADDRESS  
DECODER  
A
5
A
0
8
O
7
O
6
O
5
O
3
O
O
9
0
A
6
10  
11  
12  
1
15  
14  
O
2
O
1
O
2
O
4
O
3
A
7
COLUMN  
ADDRESS  
GND  
13  
A
8
LCC/PLCC  
Top View  
O
0
S
R
CP  
PS  
CLR  
CP  
3
2 1 2827  
4
26  
25  
E
CLR  
A
4
5
6
7
8
9
A
24  
23  
22  
21  
20  
19  
3
A
2
E
S
CP  
NC  
O
A
1
E
S
A
0
NC  
7
10  
11  
O
0
O
6
E
12 131415161718  
Selection Guide  
7C225A-25  
7C225A-30  
7C225A-40  
Unit  
ns  
Minimum Address Set-Up Time  
Maximum Clock to Output  
25  
12  
90  
30  
15  
90  
40  
25  
ns  
Maximum Operating  
Current  
Commercial  
Military  
mA  
mA  
120  
Cypress Semiconductor Corporation  
Document #: 38-04001 Rev. *B  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised October 8, 2002  

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