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CYM1841AP7-35C PDF预览

CYM1841AP7-35C

更新时间: 2024-09-17 08:03:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
14页 198K
描述
SRAM Module, 256KX32, 35ns, CMOS, PSMA72, PLASTIC, SIMM-72

CYM1841AP7-35C 数据手册

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CYM1841A  
CYM1841B  
CYM1841C  
256K x 32 Static RAM Module  
Reading or writing can be executed on individual bytes or any  
combination of multiple bytes through proper use of selects.  
Features  
• High-density 8-megabit SRAM module  
Writing to each byte is accomplished when the appropriate  
Chip Select (CS) and Write Enable (WE) inputs are both LOW.  
Data on the Input/Output pins (I/O) is written into the memory  
• 32-bit standard footprint supports densities from 16K  
x 32 through 1M x 32  
location specified on the address pins (A through A ).  
0
17  
• High-speed CMOS SRAMs  
— Access time of 12 ns  
Reading the device is accomplished by taking the Chip Select  
(CS) LOW while Write Enable (WE) remains HIGH. Under  
these conditions, the contents of the memory location speci-  
fied on the address pins will appear on the data Input/Output  
pins (I/O).  
• Low active power  
— 5.3W (max.) at 25 ns  
• SMD technology  
The data input/output pins stay at the high-impedance state  
when write enable is LOW or the appropriate chip selects are  
HIGH.  
• TTL-compatible inputs and outputs  
• Low profile  
Two pins (PD and PD ) are used to identify module memory  
0
1
— Max. height of 0.58 in.  
• Available in ZIP, SIMM, and angled SIMM footprint  
density in applications where alternate versions of the JE-  
DEC-standard modules can be interchanged.  
• 72-pin SIMM version compatible with 1M x 32  
(CYM1851)  
The CYM1841A, CYM1841B, and CYM1841C are 100% pin,  
package, and electrically identical. The CYM1841A utilizes  
corner power and ground SRAMs, the CYM1841B utilizes  
256K x 16 SRAMs, the CYM1841C utilizes center power and  
ground SRAMs.  
Functional Description  
The CYM1841A/B/C are high-performance 8-megabit static  
RAM modules organized as 256K words by 32 bits. This mod-  
ule is constructed from eight 256K x 4 SRAMs (1841A/C) or  
256K x 16 SRAMs (1841B) in SOJ packages mounted on an  
epoxy laminate board with pins. Four chip selects (CS , CS ,  
A 72-pin SIMM is offered for compatibility with the 1M x 32  
CYM1851. This version is socket upgradable to the CYM1851.  
Both the 64-pin and 72-pin SIMM modules are available with  
either tin-lead or 10 micro-inches of gold flash on the edge  
contacts.  
1
2
CS , CS ) are used to independently enable the four bytes.  
3
4
Logic Block Diagram  
PD – GND  
0
PD – GND  
PD – OPEN (72-pin only)  
2
1
A A  
0
17  
18  
PD – OPEN (72-pin only)  
3
OE  
WE  
256K x 4  
SRAM  
256K x 4  
SRAM  
I/O – I/O  
I/O – I/O  
4 7  
0
3
4
4
4
4
4
4
4
4
CS  
1
256K x 4  
SRAM  
256K x 4  
SRAM  
I/O – I/O  
I/O – I/O  
12  
8
11  
15  
23  
31  
CS  
CS  
CS  
2
3
4
256K x 4  
SRAM  
256K x 4  
SRAM  
I/O – I/O  
16  
I/O –I/O  
20  
19  
256K x 4  
SRAM  
256K x 4  
SRAM  
I/O –I/O  
28  
I/O – I/O  
24  
27  
1841A–1  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
June 13, 2000  

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