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CYDD36S72V18-167BGXC PDF预览

CYDD36S72V18-167BGXC

更新时间: 2024-02-23 17:01:26
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
53页 796K
描述
Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-484

CYDD36S72V18-167BGXC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:484
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:13 ns其他特性:PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATE AT 1.5V.
JESD-30 代码:S-PBGA-B484JESD-609代码:e1
长度:27 mm内存密度:37748736 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:72
湿度敏感等级:3功能数量:1
端子数量:484字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX72封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.46 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:27 mmBase Number Matches:1

CYDD36S72V18-167BGXC 数据手册

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FullFlex  
FullFlex™ Synchronous  
DDR Dual-Port SRAM  
— Selectable LVTTL (3.3V), Extended HSTL  
(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on  
each port  
Features  
• True dual-ported memory allows simultaneous access  
to the shared array from each port  
— Burst counters for sequential memory access  
— Mailbox with interrupt flags for message passing  
— Dual Chip Enables for easy depth expansion  
• Synchronous pipelined operation with selectable  
Double Data Rate (DDR) or Single Data Rate (SDR)  
operation on each port  
— DDR interface at 200 MHz  
Functional Description  
— SDR interface at 250 MHz  
The FullFlexDual-Port SRAM families consist of 4-Mbit,  
9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static  
RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two  
ports are provided, allowing the array to be accessed simulta-  
neously. Simultaneous access to a location triggers determin-  
istic access control. For FullFlex72, these ports can operate  
independently in DDR mode with 36-bit bus widths or in SDR  
mode with 72-bit bus widths. For FullFlex36 and FullFlex18,  
the ports operate in DDR mode only. Each port can be  
independently configured for two pipelined stages for SDR  
mode or 2.5 stages in DDR mode. Each port can also be  
configured to operate in pipelined or flow-through mode in  
SDR mode.  
— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)  
• Selectable pipelined or flow-through mode  
• 1.5V or 1.8V core power supply  
• Commercial and Industrial temperature ranges  
• IEEE 1149.1 JTAG boundary scan  
• Available in 484-ball PBGA Packages and 256-ball  
FBGA Packages  
• FullFlex72 family  
— 36 Mbit: 512K x 36 x 2 DDR or 512K x 72 SDR  
(CYDD36S72V18)  
Advanced features include built-in deterministic access  
control to manage address collisions during simultaneous  
access to the same memory location, Variable Impedance  
Matching (VIM) to improve data transmission by matching the  
output driver impedance to the line impedance, and echo  
clocks to improve data transfer.  
— 18 Mbit: 256K x 36 x 2 DDR or 256K x 72 SDR  
(CYDD18S72V18)  
— 9 Mbit: 128K x 36 x 2 DDR or 128K x 72 SDR  
(CYDD09S72V18)  
— 4 Mbit: 64K x 36 x 2 DDR or 64 x 72 SDR  
(CYDD04S72V18)  
To reduce the static power consumption, chip enables can be  
used to power down the internal circuitry. The number of  
cycles of latency before a change in CE0 or CE1 will enable  
or disable the databus matches the number of cycles of read  
latency selected for the device. In order for a valid write or read  
to occur, both chip enable inputs on a port must be active.  
• FullFlex36 family  
— 36 Mbit: 512K x 36 x 2 DDR (CYDD36S36V18)  
— 18 Mbit: 256K x 36 x 2 DDR (CYDD18S36V18)  
— 9 Mbit: 128K x 36 x 2 DDR (CYDD09S36V18)  
— 4 Mbit: 64K x 36 x 2 DDR (CYDD04S36V18)  
• FullFlex18 family  
Each port contains an optional burst counter on the input  
address register. After externally loading the counter with the  
initial address, the counter will increment the address inter-  
nally.  
— 36 Mbit: 1M x 18 x 2 DDR (CYDD36S18V18)  
— 18 Mbit: 512K x 18 x 2 DDR (CYDD18S18V18)  
— 9 Mbit: 256K x 18 x 2 DDR (CYDD09S18V18)  
— 4 Mbit: 128K x 18 x 2 DDR (CYDD04S18V18)  
Additional features of this device include a mask register and  
a
mirror register to control counter increments and  
wrap-around. The counter-interrupt (CNTINT) flags notify the  
host that the counter will reach maximum count value on the  
next clock cycle. The host can read the burst-counter internal  
address, mask register address, and busy address on the  
address lines. The host can also load the counter with the  
address stored in the mirror register by utilizing the retransmit  
functionality. Mailbox interrupt flags can be used for message  
passing, and JTAG boundary scan and asynchronous Master  
Reset (MRST) are also available. The logic block diagram in  
Figure 1 displays these features.  
• Built-in deterministic access control to manage  
address collisions  
— Deterministic flag output upon collision detection  
— Collision detection on back-to-back clock cycles  
— First Busy Address readback  
• Advanced features for improved high-speed data  
transfer and flexibility  
The FullFlex72 DDR family of devices is offered in a 484-ball  
plastic BGA package. The FullFlex36 and FullFlex18 DDR  
only families of devices are offered in both 484-ball and  
256-ball fine pitch BGA packages.  
— Variable Impedance Matching (VIM)  
— Echo clocks  
Cypress Semiconductor Corporation  
Document #: 38-06072 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 6, 2006  

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