Datasheet > CYDD04S72V18-167BGI

CYDD04S72V18-167BGI

更新时间： 2024-11-07 15:45:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
53页	2422K
描述
Dual-Port SRAM, 64KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484

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CYDD04S72V18-167BGI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484	针数：	484
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	9 ns	其他特性：	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATE AT 1.8V
最大时钟频率 (fCLK)：	167 MHz	I/O 类型：	COMMON
JESD-30 代码：	S-PBGA-B484	JESD-609代码：	e0
长度：	23 mm	内存密度：	4718592 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	72
湿度敏感等级：	3	功能数量：	1
端口数量：	2	端子数量：	484
字数：	65536 words	字数代码：	64000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	64KX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA484,22X22,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8 V	认证状态：	Not Qualified
座面最大高度：	2.16 mm	最大待机电流：	0.17 A
最小待机电流：	1.5 V	子类别：	SRAMs
最大压摆率：	0.77 mA	最大供电电压 (Vsup)：	1.58 V
最小供电电压 (Vsup)：	1.42 V	标称供电电压 (Vsup)：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	23 mm	Base Number Matches：	1

CYDD04S72V18-167BGI 数据手册

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FullFlex

FullFlex™ Synchronous

DDR Dual-Port SRAM

— Selectable LVTTL (3.3V), Extended HSTL

(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on

each port

Features

• True dual-ported memory allows simultaneous access

to the shared array from each port

— Burst counters for sequential memory access

— Mailbox with interrupt flags for message passing

— Dual Chip Enables for easy depth expansion

• Synchronous pipelined operation with selectable

Double Data Rate (DDR) or Single Data Rate (SDR)

operation on each port

— DDR interface at 200 MHz

Functional Description

— SDR interface at 250 MHz

The FullFlex™ Dual-Port SRAM families consist of 4-Mbit,

9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static

RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two

ports are provided, allowing the array to be accessed simulta-

neously. Simultaneous access to a location triggers determin-

istic access control. For FullFlex72, these ports can operate

independently in DDR mode with 36-bit bus widths or in SDR

mode with 72-bit bus widths. For FullFlex36 and FullFlex18,

the ports operate in DDR mode only. Each port can be

independently configured for two pipelined stages for SDR

mode or 2.5 stages in DDR mode. Each port can also be

configured to operate in pipelined or flow-through mode in

SDR mode.

— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)

• Selectable pipelined or flow-through mode

• 1.5V or 1.8V core power supply

• Commercial and Industrial temperature ranges

• IEEE 1149.1 JTAG boundary scan

• Available in 484-ball PBGA Packages and 256-ball

FBGA Packages

• FullFlex72 family

— 18 Mbit: 256K x 36 x 2 DDR or 256K x 72 SDR

(CYDD18S72V18)

Advanced features include built-in deterministic access

control to manage address collisions during simultaneous

access to the same memory location, Variable Impedance

Matching (VIM) to improve data transmission by matching the

output driver impedance to the line impedance, and echo

clocks to improve data transfer.

— 9 Mbit: 128K x 36 x 2 DDR or 128K x 72 SDR

(CYDD09S72V18)

— 4 Mbit: 64K x 36 x 2 DDR or 64 x 72 SDR

(CYDD04S72V18)

• FullFlex36 family

To reduce the static power consumption, chip enables can be

used to power down the internal circuitry. The number of

cycles of latency before a change in CE0 or CE1 will enable

or disable the databus matches the number of cycles of read

latency selected for the device. In order for a valid write or read

to occur, both chip enable inputs on a port must be active.

— 36 Mbit: 512K x 36 x 2 DDR (CYDD36S36V18)

— 18 Mbit: 256K x 36 x 2 DDR (CYDD18S36V18)

— 9 Mbit: 128K x 36 x 2 DDR (CYDD09S36V18)

— 4 Mbit: 64K x 36 x 2 DDR (CYDD04S36V18)

• FullFlex18 family

Each port contains an optional burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally.

— 36 Mbit: 1M x 18 x 2 DDR (CYDD36S18V18)

— 18 Mbit: 512K x 18 x 2 DDR (CYDD18S18V18)

— 9 Mbit: 256K x 18 x 2 DDR (CYDD09S18V18)

— 4 Mbit: 128K x 18 x 2 DDR (CYDD04S18V18)

Additional features of this device include a mask register and

mirror register to control counter increments and

• Built-in deterministic access control to manage

address collisions

wrap-around. The counter-interrupt (CNTINT) flags notify the

host that the counter will reach maximum count value on the

next clock cycle. The host can read the burst-counter internal

address, mask register address, and busy address on the

address lines. The host can also load the counter with the

address stored in the mirror register by utilizing the retransmit

functionality. Mailbox interrupt flags can be used for message

passing, and JTAG boundary scan and asynchronous Master

Reset (MRST) are also available. The logic block diagram in

Figure 1 displays these features.

— Deterministic flag output upon collision detection

— Collision detection on back-to-back clock cycles

— First Busy Address readback

• Advanced features for improved high-speed data

transfer and flexibility

— Variable Impedance Matching (VIM)

— Echo clocks

The FullFlex72 DDR family of devices is offered in a 484-ball

plastic BGA package. The FullFlex36 and FullFlex18 DDR

only families of devices are offered in both 484-ball and

256-ball fine pitch BGA packages.

Cypress Semiconductor Corporation

Document #: 38-06072 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 21, 2006

12 3 4 5 6 7...53

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与CYDD04S72V18-167BGI相关器件

型号	品牌	获取价格	描述	数据表
CYDD04S72V18-167BGXC	CYPRESS	获取价格	Dual-Port SRAM, 64KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD F
CYDD04S72V18-167BGXI	CYPRESS	获取价格	Dual-Port SRAM, 64KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD F
CYDD04S72V18-200BBC	CYPRESS	获取价格	Dual-Port SRAM, 64KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTI
CYDD04S72V18-200BBI	CYPRESS	获取价格	Dual-Port SRAM, 64KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTI
CYDD04S72V18-200BGXC	CYPRESS	获取价格	Dual-Port SRAM, 64KX72, 7.2ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYDD04S72V18-250BBC	CYPRESS	获取价格	Dual-Port SRAM, 64KX72, 7.2ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLAS
CYDD09S18V18-167BBC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256
CYDD09S18V18-167BBI	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256
CYDD09S18V18-167BBXC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FB
CYDD09S18V18-167BBXI	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FB

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