Datasheet > CYD36S18V18-200BGC

CYD36S18V18-200BGC

更新时间： 2024-11-08 07:49:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
52页	1093K
描述
Dual-Port SRAM, 2MX18, 9ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CYD36S18V18-200BGC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484	针数：	484
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	9 ns	其他特性：	PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	S-PBGA-B484	JESD-609代码：	e0
长度：	27 mm	内存密度：	37748736 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端口数量：	2	端子数量：	484
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA484,22X22,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8 V	认证状态：	Not Qualified
座面最大高度：	2.46 mm	最大待机电流：	0.59 A
最小待机电流：	1.4 V	子类别：	SRAMs
最大压摆率：	1.43 mA	最大供电电压 (Vsup)：	1.58 V
最小供电电压 (Vsup)：	1.42 V	标称供电电压 (Vsup)：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	27 mm	Base Number Matches：	1

CYD36S18V18-200BGC 数据手册

浏览型号CYD36S18V18-200BGC的Datasheet PDF文件第2页

浏览型号CYD36S18V18-200BGC的Datasheet PDF文件第3页

浏览型号CYD36S18V18-200BGC的Datasheet PDF文件第4页

浏览型号CYD36S18V18-200BGC的Datasheet PDF文件第5页

浏览型号CYD36S18V18-200BGC的Datasheet PDF文件第6页

浏览型号CYD36S18V18-200BGC的Datasheet PDF文件第7页

FullFlex

FullFlex™ Synchronous SDR Dual Port SRAM

Features

Functional Description

■ True dual port memory enables simultaneous access to the

shared array from each port

The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,

9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static

RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two

ports are provided, enabling simultaneous access to the array.

Simultaneous access to a location triggers deterministic access

control. For FullFlex72 these ports operate independently with

72-bit bus widths and each port is independently configured for

two pipelined stages. Each port is also configured to operate in

pipelined or flow through mode.

■ Synchronous pipelined operation with Single Data Rate (SDR)

operation on each port

❐ SDR interface at 200 MHz

❐ Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)

■ Selectable pipelined or flow-through mode

■ 1.5V or 1.8V core power supply

The advanced features include the following:

■ Commercial and Industrial temperature

■ IEEE 1149.1 JTAG boundary scan

■ Built in deterministic access control to manage address colli-

sions during simultaneous access tothesamememorylocation

■ Variable Impedance Matching (VIM) to improve data trans-

mission by matching the output driver impedance to the line

impedance

■ Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and

x18) packages

■ FullFlex72 family

■ Echo clocks to improve data transfer

❐ 36 Mbit: 512K x 72 (CYD36S72V18)

❐ 18 Mbit: 256K x 72 (CYD18S72V18)

❐ 9 Mbit: 128K x 72 (CYD09S72V18)

❐ 4 Mbit: 64K x 72 (CYD04S72V18)

To reduce the static power consumption, chip enables power

down the internal circuitry. The number of latency cycles before

a change in CE0 or CE1 enables or disables the databus

matches the number of cycles of read latency selected for the

device. For a valid write or read to occur, activate both chip

enable inputs on a port.

■ FullFlex36 family

❐ 36 Mbit: 1M x 36 (CYD36S36V18)

❐ 18 Mbit: 512K x 36 (CYD18S36V18)

❐ 9 Mbit: 256K x 36 (CYD09S36V18)

❐ 4 Mbit: 128K x 36 (CYD04S36V18)

❐ 2 Mbit: 64K x 36 (CYD02S36V18)

Each port contains an optional burst counter on the input address

address, the counter increments the address internally.

Additional device features include a mask register and a mirror

counter interrupt (CNTINT) flags notify the host that the counter

reaches maximum count value on the next clock cycle. The host

reads the burst counter internal address, mask register address,

and busy address on the address lines. The host also loads the

counter with the address stored in the mirror register by using the

retransmit functionality. Mailbox interrupt flags are used for

message passing, and JTAG boundary scan and asynchronous

Master Reset (MRST) are also available. The Logic Block

Diagram on page 2 shows these features.

■ FullFlex18 family

❐ 36 Mbit: 2M x 18 (CYD36S18V18)

❐ 18 Mbit: 1M x 18 (CYD18S18V18)

❐ 9 Mbit: 512K x 18 (CYD09S18V18)

❐ 4 Mbit: 256K x 18 (CYD04S18V18)

■ Built in deterministic access control to manage address colli-

sions

❐ Deterministic flag output upon collision detection

❐ Collision detection on back-to-back clock cycles

❐ First Busy Address readback

The FullFlex72 is offered in a 484-Ball plastic BGA package. The

FullFlex36 and FullFlex18 are available in 256-Ball fine pitch

BGA package.

■ Advanced features for improved high speed data transfer and

flexibility

❐ Variable Impedance Matching (VIM)

❐ Echo clocks

❐ Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V

LVCMOS, or 2.5V LVCMOS IO on each port

❐ Burst counters for sequential memory access

❐ Mailbox with interrupt flags for message passing

❐ Dual Chip Enables for easy depth expansion

Cypress Semiconductor Corporation

Document Number: 38-06082 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 15, 2008

[+] Feedback

12 3 4 5 6 7...52

中文翻译

下载PDF

与CYD36S18V18-200BGC相关器件

型号	品牌	获取价格	描述	数据表
CYD36S36V18	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM
CYD36S36V18-133BBI	CYPRESS	获取价格	Dual-Port SRAM, 1MX36, 4.5ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLAST
CYD36S36V18-167BBC	CYPRESS	获取价格	暂无描述
CYD36S36V18-167BBI	CYPRESS	获取价格	Dual-Port SRAM, 1MX36, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC
CYD36S36V18-167BBXI	CYPRESS	获取价格	Dual-Port SRAM, 1MX36, 4ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD FR
CYD36S36V18-167BGC	CYPRESS	获取价格	Dual-Port SRAM, 1MX36, 11ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLASTI
CYD36S36V18-167BGXC	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD36S36V18-167BGXI	CYPRESS	获取价格	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD36S36V18-200BBXC	CYPRESS	获取价格	Dual-Port SRAM, 1MX36, 3.3ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD
CYD36S36V18-200BGC	CYPRESS	获取价格	暂无描述

与CYD36S18V18-200BGC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

16
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

CYD36S18V18-200BGC

CYD36S18V18-200BGC 技术参数

CYD36S18V18-200BGC 数据手册

与CYD36S18V18-200BGC相关器件

与CYD36S18V18-200BGC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CYD36S18V18-200BGC

CYD36S18V18-200BGC 技术参数

CYD36S18V18-200BGC 数据手册

与CYD36S18V18-200BGC相关器件

与CYD36S18V18-200BGC相关文章

您还可以找

您在本页遇到什么问题？