5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CYD18S36V18-200BBAI
CYD18S36V18-200BBAI PDF预览

CYD18S36V18-200BBAI

更新时间： 2024-11-27 13:07:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
52页 1327K
描述
Dual-Port SRAM, 512KX36, 3.3ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256

阅读下载

中文翻译

获取价格

CYD18S36V18-200BBAI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256
针数：256Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.65Is Samacsys：N
最长访问时间：3.3 ns其他特性：PIPELINED OR FLOW-THROUGH ARCHITECTURE, IT CAN ALSO OPERATES AT 1.8V
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：S-PBGA-B256JESD-609代码：e0
长度：17 mm内存密度：18874368 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端口数量：2端子数量：256
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA256,16X16,40
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：1.5/1.8 V认证状态：Not Qualified
座面最大高度：1.7 mm最大待机电流：0.35 A
最小待机电流：1.4 V子类别：SRAMs
最大压摆率：0.86 mA最大供电电压 (Vsup)：1.58 V
最小供电电压 (Vsup)：1.42 V标称供电电压 (Vsup)：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：17 mmBase Number Matches：1

CYD18S36V18-200BBAI 数据手册

 浏览型号CYD18S36V18-200BBAI的Datasheet PDF文件第2页浏览型号CYD18S36V18-200BBAI的Datasheet PDF文件第3页浏览型号CYD18S36V18-200BBAI的Datasheet PDF文件第4页浏览型号CYD18S36V18-200BBAI的Datasheet PDF文件第5页浏览型号CYD18S36V18-200BBAI的Datasheet PDF文件第6页浏览型号CYD18S36V18-200BBAI的Datasheet PDF文件第7页 
FullFlex  
FullFlexTM Synchronous SDR  
Dual Port SRAM  
FullFlex™ Synchronous SDR Dual Port SRAM  
Features  
Functional Description  
■ True dual port memory enables simultaneous access to the  
shared array from each port  
The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit,  
18-Mbit, and 36-Mbit synchronous, true dual port static RAMs  
that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports  
are provided, enabling simultaneous access to the array.  
Simultaneous access to a location triggers deterministic access  
control. For FullFlex72 these ports operate independently with  
72-bit bus widths and each port is independently configured for  
two pipelined stages. Each port is also configured to operate in  
pipelined or flow through mode.  
■ Synchronous pipelined operation with single data rate (SDR)  
operation on each port  
❐ SDR interface at 200 MHz  
❐ Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)  
■ Selectable pipelined or flow-through mode  
■ 1.5 V or 1.8 V core power supply  
The advanced features include the following:  
■ Commercial and Industrial temperature  
■ IEEE 1149.1 JTAG boundary scan  
■ Built in deterministic access control to manage address  
collisions during simultaneous access to the same memory  
location  
■ Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36  
and × 18) packages  
■ Variable Impedance Matching (VIM) to improve data  
transmission by matching the output driver impedance to the  
line impedance  
■ FullFlex72 family  
❐ 36-Mbit: 512 K × 72 (CYD36S72V18)  
❐ 18-Mbit: 256 K × 72 (CYD18S72V18)  
❐ 9-Mbit: 128 K × 72 (CYD09S72V18)  
■ Echo clocks to improve data transfer  
To reduce the static power consumption, chip enables power  
down the internal circuitry. The number of latency cycles before  
a change in CE0 or CE1 enables or disables the databus  
matches the number of cycles of read latency selected for the  
device. For a valid write or read to occur, activate both chip  
enable inputs on a port.  
■ FullFlex36 family  
❐ 36-Mbit: 1 M × 36 (CYD36S36V18)  
❐ 18-Mbit: 512 K × 36 (CYD18S36V18)  
❐ 9-Mbit: 256 K × 36 (CYD09S36V18)  
❐ 2-Mbit: 64 K × 36 (CYD02S36V18)  
Each port contains an optional burst counter on the input address  
register. After externally loading the counter with the initial  
address, the counter increments the address internally.  
■ FullFlex18 family  
❐ 36-Mbit: 2 M × 18 (CYD36S18V18)  
❐ 18-Mbit: 1 M × 18 (CYD18S18V18)  
❐ 9-Mbit: 512 K × 18 (CYD09S18V18)  
Additional device features include a mask register and a mirror  
register to control counter increments and wrap around. The  
counter interrupt (CNTINT) flags notify the host that the counter  
reaches maximum count value on the next clock cycle. The host  
reads the burst counter internal address, mask register address,  
and busy address on the address lines. The host also loads the  
counter with the address stored in the mirror register by using the  
retransmit functionality. Mailbox interrupt flags are used for  
message passing, and JTAG boundary scan and asynchronous  
Master Reset (MRST) are also available. The Logic Block  
Diagram on page 2 shows these features.  
■ Built in deterministic access control to manage address  
collisions  
❐ Deterministic flag output upon collision detection  
❐ Collision detection on back-to-back clock cycles  
❐ First busy address readback  
■ Advanced features for improved high speed data transfer and  
flexibility  
❐ Variable impedance matching (VIM)  
❐ Echo clocks  
❐ Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V),  
1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port  
❐ Burst counters for sequential memory access  
❐ Mailbox with interrupt flags for message passing  
❐ Dual chip enables for easy depth expansion  
The FullFlex72 is offered in a 484-ball plastic BGA package. The  
FullFlex36 and FullFlex18 are available in 256-ball fine pitch  
BGA package except the 36-Mbit devices which are offered in  
484-ball plastic BGA package.  
Cypress Semiconductor Corporation  
Document Number: 38-06082 Rev. *K  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 31, 2011  
[+] Feedback  
1234567...52

中文翻译

下载PDF

与CYD18S36V18-200BBAI相关器件

型号 品牌 获取价格 描述 数据表
CYD18S36V18-200BBAXI CYPRESS

获取价格

 		FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
CYD18S36V18-200BBC CYPRESS

获取价格

 		Dual-Port SRAM, 512KX36, 9ns, CMOS, PBGA256, 19 X 19 MM, 1.70 MM HEIGHT, 1 MM PITCH, FBGA-
CYD18S36V18-200BBI CYPRESS

获取价格

 		Dual-Port SRAM, 512KX36, 9ns, CMOS, PBGA256, 19 X 19 MM, 1.70 MM HEIGHT, 1 MM PITCH, FBGA-
CYD18S36V18-200BBXC CYPRESS

获取价格

 		Dual-Port SRAM, 512KX36, 9ns, CMOS, PBGA256, 19 X 19 MM, 1.70 MM HEIGHT, 1 MM PITCH, LEAD
CYD18S36V18-200BBXI CYPRESS

获取价格

 		暂无描述
CYD18S36V18-250BBXC CYPRESS

获取价格

 		Dual-Port SRAM, 512KX36, 7.2ns, CMOS, PBGA256, 19 X 19 MM, 1.70 MM HEIGHT, 1 MM PITCH, LEA
CYD18S72V CYPRESS

获取价格

 		FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-100BBC CYPRESS

获取价格

 		FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-100BBI CYPRESS

获取价格

 		FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
CYD18S72V-100BBXC CYPRESS

获取价格

 		FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous D

与CYD18S36V18-200BBAI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证