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CY91F467DAPFVS-GS-UJE2 PDF预览

CY91F467DAPFVS-GS-UJE2

更新时间: 2024-09-22 01:07:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器
页数 文件大小 规格书
138页 2385K
描述
FR60 32-bit Microcontroller

CY91F467DAPFVS-GS-UJE2 数据手册

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CY91460D Series  
FR60 32-bit Microcontroller  
CY91460D series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require  
high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which  
is compatible with the FR family of CPUs.  
This series contains the LIN-USART and CAN controllers.  
Features  
Bit search module (for REALOS)  
Function to search from the MSB (most significant bit) for the  
position of the first “0”, “1”, or changed bit in a word  
FR60 CPU Core  
32-bit RISC, load/store architecture, five-stage pipeline  
16-bit fixed-length instructions (basic instructions)  
Instruction execution speed: 1 instruction per cycle  
LIN-USART (full duplex double buffer): 5 channels  
Clock synchronous/asynchronous selectable  
Sync-break detection  
Instructions including memory-to-memory transfer, bit  
manipulation, and barrel shift instructions: Instructions suitable  
for embedded applications  
Internal dedicated baud rate generator  
I2C bus interface (supports 400 kbps): 3 channels  
Master/slave transmission and reception  
Arbitration function, clock synchronization function  
Function entry/exit instructions and register data multi-load  
store instructions : Instructions supporting C language  
CAN controller (C-CAN): 3 channels  
Maximum transfer speed: 1 Mbps  
32 transmission/reception message buffers  
Register interlock function: Facilitating assembly-language  
coding  
Built-in multiplier with instruction-level support  
Signed 32-bit multiplication: 5 cycles  
Signed 16-bit multiplication: 3 cycles  
Stepper motor controller : 6 channels  
4 high current output to each channel  
2 synchronized PWMs per channel (8/10-bit)  
Interrupts (save PC/PS) : 6 cycles (16 priority levels)  
Sound generator : 1 channel  
To1n)efrequency:PWMfrequencydivide-by-two(reloadvalue  
Harvard architecture enabling program access and data  
access to be performed simultaneously  
Alarm comparator : 1 channel  
Monitor external voltage  
Instructions compatible with the FR family  
Internal Peripheral Resources  
General-purpose ports : Maximum 170 ports  
DMAC (DMA Controller)  
Maximum of 5 channels able to operate simultaneously.  
(External to external : 1 channel)  
3 transfer sources (external pin/internal peripheral/software)  
Activation source can be selected using software.  
Addressing mode specifies full 32-bit addresses  
(increment/decrement/fixed)  
Generate an interrupt in case of voltage lower/higher than  
the defined thresholds (reference voltage)  
16-bit PPG timer : 12 channels  
16-bit PFM timer : 1 channel  
16-bit reload timer: 8 channels  
16-bit free-run timer: 8 channels (1 channel each for ICU and  
OCU)  
Input capture: 8 channels (operates in conjunction with the  
free-run timer)  
Transfer mode (demand transfer/burst transfer/step  
transfer/block transfer)  
Output compare: 4 channels (operates in conjunction with the  
free-run timer)  
Fly-by transfer support (between external I/O and memory)  
Transfer data size selectable from 8/16/32-bit  
Multi-byte transfer enabled (by software)  
Up/Down counter: 3 channels (3*8-bit or 1*16-bit + 1*8-bit)  
Watchdog timer  
DMAC descriptor in I/O areas (200 to 240 , 1000 to  
H
H
H
1024 )  
H
A/D converter (successive approximation type)  
10-bit resolution: 24 channels  
Conversion time: minimum 1 s  
External interrupt inputs : 14 channels  
8 channels shared with CAN RX or I2C pins  
Real-time clock  
Low-power consumption modes : Sleep/stop mode function  
Supply Supervisor: Low voltage detection circuit for external  
VDD5 and internal 1.8V core voltage  
Cypress Semiconductor Corporation  
Document Number: 002-04613 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 17, 2017  

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