Cypress Semiconductor
Preliminary Data Sheet
CY8C9520,
CY8C9540, and CY8C9560
20-, 40-, and 60-Bit I/O Expander with EEPROM
Features
Overview
■ I2C™ interface logic electrically compatible with SMBus.
The CY8C95xx is a multi-port I/O expander with on-board user-
available EEPROM and several PWM outputs. All devices in
this family operate identically but differ in I/O pins, number of
PWMs, and internal EEPROM size.
■ Up to 20 (CY8C9520), 40 (CY8C9540) or 60 (CY8C9560)
I/O data pins independently configurable as inputs, outputs,
bi-directional input/outputs or PWM outputs.
■ 4/8/16 PWM sources with 8-bit resolution.
The CY8C95xx operates as two I2C slave devices. The first
device is a multi-port I/O expander (single I2C address to
access all ports via registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to dis-
able the EEPROM. The EEPROM utilizes 2-byte addressing to
support the 28-Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
■ Extendable Soft Addressing™ algorithm allowing flexible
I2C-address configuration.
■ Internal 3-/11-/27-Kbyte EEPROM.
■ Storage of user defaults and I/O port settings in the internal
EEPROM.
■ Optional EEPROM Write Disable (WD) input.
■ Interrupt output indicates input pin level changes and pulse
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM
ouputs. The individual data pins can be configured as open
drain/collector, strong drive (10 mA source, 25 mA sink), resis-
tively pulled-up/-down, or high-impedance. The factory default
configuration is pulled-up internally.
width modulator (PWM) state changes.
■ Internal power-on reset (POR).
WD
EEPROM
User
Settings
Area
User
Available
Area
The system master writes to the I/O configuration registers via
the I2C bus. Configuration and output register settings can be
stored as user defaults in a dedicated section of the EEPROM.
If user defaults have been stored in EEPROM, they are
restored to the ports at power-up. While this device can share
the bus with SMBus devices, it can only communicate with
I2C-masters.
Clocks
32 kHz
24 MHz
GPort 0
GPort 1
GPort 2
GPort 3
8 Bit I/O
5 Bit I/O
There is one dedicated pin that is configured as an interrupt out-
put (INT) and can be connected to the interrupt logic of the sys-
tem master. This signal can inform the system master that there
is incoming data on its ports or that the PWM output state was
changed.
1.5 MHz
3 Bit I/O
or A4-A6
93.75 kHz
4 Bit I/O
or A1-A3,
Divider (1-255)
Control
Unit
The EEPROM is byte-readable and supports byte-by-byte writ-
ing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The con-
figuration registers can also disable EEPROM operations.
PWM 0
8 Bit I/O
8 Bit I/O
PWM 15
GPort 7
The CY8C95xx has one fixed address pin (A0) and up to six
additional pins (A1-A6) which allow up to 128 devices to share a
common two-wire I2C data bus. The Extendable Soft Address-
ing algorithm provides the option to choose the number of pins
needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
SCL
SDA
INT
A0
Vdd
Vss
Power-on-Reset
Figure 1-1. Top Level Block Diagram
August 17, 2005
© Cypress Semiconductor Corp. 2005 — Document No. 38-12036 Rev. *A
1