Datasheet > CY8C5387PVI-036

CY8C5387PVI-036

更新时间： 2024-11-11 20:10:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟光电二极管
页数	文件大小	规格书
102页	2374K
描述
Multifunction Peripheral, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, SSOP-48

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CY8C5387PVI-036 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	0.300 INCH, ROHS COMPLIANT, SSOP-48	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	地址总线宽度：
边界扫描：	YES	最大时钟频率：	80 MHz
外部数据总线宽度：		JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e3	长度：	15.875 mm
湿度敏感等级：	3	I/O 线路数量：	31
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP48,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	2/5 V
认证状态：	Not Qualified	RAM（字数）：	16384
ROM大小（位）：	1048576 Bits	座面最大高度：	2.79 mm
子类别：	Other Microprocessor ICs	最大供电电压：	5.5 V
最小供电电压：	1.71 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	20
紫外线可擦：	N	宽度：	7.505 mm
Base Number Matches：	1

CY8C5387PVI-036 数据手册

PRELIMINARY

PSoC^®5: CY8C53 Family Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

With its unique array of configurable blocks, PSoC^®5 is a true system level solution providing microcontroller unit (MCU), memory,

analog, and digital peripheral functions in a single chip. The CY8C53 family offers a modern method of signal acquisition, signal

processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples

(near DC voltages) to ultrasonic signals. The CY8C53 family can handle dozens of data acquisition channels and analog inputs on

every GPIO pin. The CY8C53 family is also a high-performance configurable digital system with some part numbers including

interfaces such as USB, multi-master I²C, and controller area network (CAN). In addition to communication interfaces, the CY8C53

family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM^®Cortex™-M3

microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean

primitives using PSoC^®Creator™, a hierarchical schematic design entry tool. The CY8C53 family provides unparalleled opportunities

for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware

updates.

 Library of advanced peripherals

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

Features

 32-bit ARM Cortex-M3 CPU core

 DC to 80 MHz operation

 Flash program memory, up to 256 KB, 100,000 write cycles,

• Quadrature decoder

20-year retention, multiple security features

 Analog peripherals (1.71 V  V_DDA 5.5 V)

 Up to 64 KB SRAM memory

 1.024 V ± 0.1% internal voltage reference across –40 °C to

 2-KB electrically erasable programmable read-only memory

+85 °C (14 ppm/°C)

(EEPROM) memory, 1 million cycles, and 20 years retention

 24-channel direct memory access (DMA) with multilayer

AMBA high-performance bus (AHB) bus access

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

 Successive approximation register (SAR) analog-to-digital

converter (ADC), 12-bit at 1 Msps

 Two 8-bit 8 Msps current digital-to-analog converters (DAC)

(IDACs) or 1 Msps voltage DACs (VDACs)

 Four comparators with 95-ns response time

 Low voltage, ultra low power

 Two uncommitted opamps with 25-mA drive capability

 Two configurable multifunction analog blocks. Example

configurations are programmable gain amplifier (PGA),

transimpedance amplifier (TIA), mixer, and sample and hold

 CapSense support

 Wide operating voltage range: 0.5 V to 5.5 V

 High efficiency boost regulator from 0.5 V input to 1.8 V to

5.0 V output

 2 mA at 6 MHz

 Low power modes including:

 Programming, debug, and trace

• 2-µA sleep mode with real time clock (RTC) and

low-voltage detect (LVD) interrupt

• 300-nA hibernate mode with RAM retention

 JTAG (4-wire), serial wire debug (SWD) (2-wire), single-wire

viewer (SWV), and TRACEPORT interfaces

 Cortex-M3 flash patch and breakpoint (FPB) block

 Cortex-M3 Embedded Trace Macrocell™ (ETM™)

generates an instruction trace stream.

 Cortex-M3 data watchpoint and trace (DWT) generates data

trace information

 Cortex-M3 instrumentation trace macrocell (ITM) can be

used for printf-style debugging

 Versatile I/O system

 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs^[1]

 Any GPIO to any digital or analog peripheral routability

 LCD direct drive from any GPIO, up to 46x16 segments

 CapSense^®support from any GPIO^[2]

 1.2 V to 5.5 V I/O interface voltages, up to 4 domains

 Maskable, independent IRQ on any pin or port

 Schmitt-trigger transistor-transistor logic (TTL) inputs

 All GPIOs configurable as open drain high/low,

pull-up/pull-down, High-Z, or strong output

 Configurable GPIO pin state at power-on reset (POR)

 25 mA sink on SIO

)

 DWT, ETM, andITMblockscommunicatewithoff-chipdebug

and trace systems via the SWV or TRACEPORT

 Bootloader programming supportable through I²C, SPI,

UART, USB, and other interfaces

 Precision, programmable clocking

 3- to 74-MHz internal oscillator over full temperature and

voltage range

 4- to 33-MHz crystal oscillator for crystal PPM accuracy

 Internal PLL clock generation up to 80 MHz

 32.768-kHz watch crystal oscillator

 Digital peripherals

 20 to 24 programmable logic device (PLD) based universal

digital blocks (UDBs)

 Full CAN 2.0b 16 RX, 8 TX buffers^[1]

 Low power internal oscillator at 1, 33, and 100 kHz

 Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator^[1]

 Up to four 16-bit configurable timer, counter, and PWM blocks

 Library of standard peripherals

 Temperature and packaging

 –40°C to +85°C degrees industrial temperature

 48-pin SSOP, 68-pin QFN, and 100-pin TQFP package

options

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• SPI, UART, and I²C

• Many others available in catalog

Notes

1. This feature on select devices only. See Ordering Information on page 91 for details.

2. GPIOs with opamp outputs are not recommended for use with CapSense

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document Number: 001-55035 Rev. *G

Revised September 2, 2010

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与CY8C5387PVI-036相关器件

型号	品牌	获取价格	描述	数据表
CY8C5388AXI-088	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5388AXI-106	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-02
CY8C5388LTI-032	CYPRESS	获取价格	Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
CY8C5388PVI-016	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, SSOP-48
CY8C5388PVI-027	CYPRESS	获取价格	Multifunction Peripheral, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, SSOP-48
CY8C54	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C54_11	CYPRESS	获取价格	Programmable System-on-Chip (PSoC?)
CY8C54_1106	CYPRESS	获取价格	Programmable System-on-Chip (PSoC) DC to 67 MHz operation
CY8C5466AXI-064	CYPRESS	获取价格	Programmable System-on-Chip (PSoC?)
CY8C5466AXI-064T	CYPRESS	获取价格	Micro Peripheral IC, CMOS, PQFP100

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