PSoC® 3: CY8C36 Family
Data Sheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C36 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, multi-master inter-integrated circuit (I2C), and controller area network (CAN). In
addition to communication interfaces, the CY8C36 family has an easy to configure logic array, flexible routing to all I/O pins, and
current DAC a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich
library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C36
family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute
design changes through simple firmware updates.
67-MHz, 24-bit fixed point digital filter block (DFB) to
Features
implement finite impulse response (FIR) and infinite impulse
Single cycle 8051 CPU core
response (IIR) filters
Library of standard peripherals
DC to 67 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
512-byte flash cache
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
read-only memory (EEPROM), 1 M cycles, and 20 years
retention
• Quadrature decoder
Analog peripherals (1.71 V VDDA 5.5 V)
24-channel direct memory access (DMA) with multilayer
1.024 V ± 0.1% internal voltage reference across –40 °C to
AHB[1] bus access
+85 °C
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
Low voltage, ultra low-power
Wide operating voltage range: 0.5 V to 5.5 V
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
High efficiency boost regulator from 0.5-V input through
Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs
1.8-V to 5.0-V output
Four comparators with 95-ns response time
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz
Up to four uncommitted opamps with 25 mA drive capability
Low-power modes including:
Up to four configurable multifunction analog blocks. Example
• 1-µA sleep mode with real-time clock (RTC) and
configurations are programmable gain amplifier (PGA),
low-voltage detect (LVD) interrupt
transimpedance amplifier (TIA), mixer, and sample and hold
• 200-nA hibernate mode with RAM retention
CapSense support
Versatile I/O system
Programming, debug, and trace
28 to 72 I/O (62 GPIOs, eightspecial input/outputs (SIO), two
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
USBIOs[2]
wire viewer (SWV) interfaces
Any GPIO to any digital or analog peripheral routability
Eight address and one data breakpoint
LCD direct drive from any GPIO, up to 46 × 16 segments[2]
4-KB instruction trace buffer
CapSense® support from any GPIO[3]
Bootloader programming supportable through I2C, SPI,
1.2-V to 5.5-V I/O interface voltages, up to four domains
UART, USB, and other interfaces
Maskable, independent interrupt request (IRQ) on any pin or
Precision, programmable clocking
port
3- to 62-MHz internal oscillator over full temperature and
Schmitt-trigger transistor-transistor logic (TTL) inputs
voltage range
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 67 MHz
32.768 kHz watch crystal oscillator
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Low-power internal oscillator at 1, 33, and 100 kHz
Digital peripherals
Temperature and packaging
20 to 24 programmable logic devices (PLD) based universal
digital blocks (UDB)
–40 °C to +85 °C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
Full CAN 2.0b 16-receive (Rx), 8-transmit (Tx) buffers[2]
package options
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[2]
Up to four 16-bit configurable timer, counter, and PWM blocks
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 116 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-53413 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 18, 2012
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