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CY8C3244LTI-135

更新时间： 2024-11-19 09:45:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器时钟
页数 文件大小 规格书
119页 3926K
描述
Programmable System-on-Chip (PSoC?)

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CY8C3244LTI-135 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：ROHS COMPLIANT, MO-220, QFN-48
针数：48Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.56
Is Samacsys：N位大小：8
边界扫描：YES总线兼容性：I2C; USB
最大时钟频率：50 MHzJESD-30 代码：S-XQCC-N48
JESD-609代码：e4长度：7 mm
湿度敏感等级：3I/O 线路数量：25
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：1.8/5 V
认证状态：Not QualifiedRAM（字数）：2000
ROM（单词）：16384ROM可编程性：FLASH
ROM大小（位）：131072 Bits座面最大高度：1 mm
速度：50 MHz子类别：Other uPs/uCs/Peripheral ICs
最大供电电压：5.5 V最小供电电压：1.71 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20紫外线可擦：N
宽度：7 mmBase Number Matches：1

CY8C3244LTI-135 数据手册

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PSoC® 3: CY8C32 Family  
Data Sheet  
Programmable System-on-Chip (PSoC®)  
General Description  
With its unique array of configurable blocks, PSoC® 3 is a true ystem level solution providing microcontroller unit (MCU), memory,  
analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal  
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples  
(near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on  
every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some  
part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I2C). In addition to communication interfaces,  
the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051  
microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives  
using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog  
and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.  
Features  
„ Single cycle 8051 CPU core  
‡ DC to 50 MHz operation  
‡ Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2]  
‡ Up to four 16-bit configurable timer, counter, and PWM blocks  
‡ Library of standard peripherals  
‡ Multiply and divide instructions  
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs  
• Serial peripheral interface (SPI), universal asynchronous  
transmitter receiver (UART), and I2C  
‡ Flash program memory, up to 64 KB, 100,000 write cycles,  
20 years retention, and multiple security features  
‡ Up to 8-KB flash error correcting code (ECC) or configuration  
storage  
• Many others available in catalog  
‡ Library of advanced peripherals  
• Cyclic redundancy check (CRC)  
• Pseudo random sequence (PRS) generator  
• Local interconnect network (LIN) bus 2.0  
• Quadrature decoder  
„ Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)  
‡ 1.024 V ±0.9-percent internal voltage reference across –40°C  
to +85°C (14 ppm/°C)  
‡ Up to 8 KB SRAM  
‡ Up to 2 KB electrically erasable programmable read-only  
memory (EEPROM), 1 M cycles, and 20 years retention  
‡ 24-channel direct memory access (DMA) with multilayer  
AHB[1] bus access  
• Programmable chained descriptors and priorities  
• High bandwidth 32-bit transfer support  
„ Low voltage, ultra low-power  
‡ Wide operating voltage range: 0.5 V to 5.5 V  
‡ High efficiency boost regulator from 0.5-V through 1.8-V to  
5.0-V output  
‡ Configurable delta-sigma ADC with 8- to12-bit resolution  
• Programmable gain stage: ×0.25 to ×16  
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion  
ratio (SINAD), ±1-bit INL/DNL  
‡ One 8-bit, 8-Msps IDAC or 1-Msps VDAC  
‡ Two comparators with 95 ns response time  
‡ CapSense support  
‡ 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz  
‡ Low-power modes including:  
• 1-µA sleep mode with real-time clock (RTC) and  
low-voltage detect (LVD) interrupt  
• 200-nA hibernate mode with RAM retention  
„ Programming, debug, and trace  
„ Versatile I/O system  
‡ JTAG (4-wire), serial wire debug (SWD) (2-wire), and single  
wire viewer (SWV) interfaces  
‡ 28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),  
two USBIOs[2]  
)
‡ Eight address and one data breakpoint  
‡ 4-KB instruction trace buffer  
‡ Any GPIO to any digital or analog peripheral routability  
‡ LCD direct drive from any GPIO, up to 46×16 segments[2]  
‡ CapSense® support from any GPIO[3]  
‡ 1.2-V to 5.5-V I/O interface voltages, up to four domains  
‡ Maskable, independent IRQ on any pin or port  
‡ Schmitt-trigger transistor-transistor logic (TTL) inputs  
‡ All GPIO configurable as open drain high/low,  
pull-up/pull-down, High Z, or strong output  
‡ Configurable GPIO pin state at power-on reset (POR)  
‡ 25 mA sink on SIO  
„ Digital peripherals  
‡ Bootloader programming supportable through I2C, SPI,  
UART, USB, and other interfaces  
„ Precision, programmable clocking  
‡ 3- to 24-MHz internal oscillator over full temperature and  
voltage range  
‡ 4- to 25-MHz crystal oscillator for crystal PPM accuracy  
‡ Internal PLL clock generation up to 50 MHz  
‡ 32.768-kHz watch crystal oscillator  
‡ Low-power internal oscillator at 1, 33, and 100 kHz  
„ Temperature and packaging  
‡ –40°C to +85°C degrees industrial temperature  
‡ 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP  
package options  
‡ 16 to 24 programmable PLD based universal digital  
blocks (UDB)  
Notes  
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus  
2. This feature on select devices only. See Ordering Information on page 106 for details.  
3. GPIOs with opamp outputs are not recommended for use with CapSense.  
Cypress Semiconductor Corporation  
Document Number: 001-56955 Rev. *J  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 30, 2011  
[+] Feedback  
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中文翻译

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