PSoC® Mixed-Signal Array
Final Data Sheet
CY8C21234, CY8C21334,
CY8C21434, CY8C21534, and CY8C21634
Features
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Powerful Harvard Architecture Processor
■
Flexible On-Chip Memory
■
Programmable Pin Configurations
❐
❐
❐
❐
M8C Processor Speeds to 24 MHz
Low Power at High Speed
❐
8K Flash Program Storage 50,000 Erase/Write
Cycles
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❐
25 mA Drive on All GPIO
Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
❐
❐
❐
❐
❐
512 Bytes SRAM Data Storage
In-System Serial Programming (ISSP™)
Partial Flash Updates
2.4V to 5.25V Operating Voltage
❐
❐
Up to 8 Analog Inputs on GPIO
Operating Voltages Down to 1.0V Using
On-Chip Switch Mode Pump (SMP)
Configurable Interrupt on All GPIO
❐
Industrial Temperature Range: -40°C to +85°C
Flexible Protection Modes
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■
Versatile Analog Mux
EEPROM Emulation in Flash
❐
❐
❐
Common Internal Analog Bus
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Advanced Peripherals (PSoC Blocks)
Simultaneous Connection of IO Combinations
Capacitive Sensing Application Capability
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Complete Development Tools
❐
4 Analog Type “E” PSoC Blocks Provide:
- 2 Comparators with DAC Refs
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Free Development Software
(PSoC Designer™)
Additional System Resources
- Single or Dual 8-Bit 28 Channel ADC
4 Digital PSoC Blocks Provide:
❐
Full-Featured, In-Circuit Emulator and
Programmer
2
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❐
I C™ Master, Slave and Multi-Master to
400 kHz
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
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❐
❐
Full Speed Emulation
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❐
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Watchdog and Sleep Timers
Complex Breakpoint Structure
128K Trace Memory
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
Complex Peripherals by Combining Blocks
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Precision, Programmable Clocking
On-Chip Precision Voltage Reference
❐
❐
❐
Internal ±2.5% 24/48 MHz Oscillator
Internal Oscillator for Watchdog and Sleep
PSoC® Functional Overview
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each CY8C21x34 PSoC device
includes four digital blocks and four analog blocks. Depending
on the PSoC package, up to 28 general purpose IO (GPIO) are
also included. The GPIO provide access to the global digital
and analog interconnects.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
January 12, 2007
© Cypress Semiconductor Corp. 2004-2007 — Document No. 38-12025 Rev. *K
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