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CY8C20324 PDF预览

CY8C20324

更新时间: 2024-11-27 06:51:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
34页 1048K
描述
CapSense PSoC Programmable System-on-Chip

CY8C20324 数据手册

 浏览型号CY8C20324的Datasheet PDF文件第2页浏览型号CY8C20324的Datasheet PDF文件第3页浏览型号CY8C20324的Datasheet PDF文件第4页浏览型号CY8C20324的Datasheet PDF文件第5页浏览型号CY8C20324的Datasheet PDF文件第6页浏览型号CY8C20324的Datasheet PDF文件第7页 
CY8C20224, CY8C20324  
CY8C20424, CY8C20524  
®
CapSense™ PSoC Programmable  
System-on-Chip™  
High Performance CapSense  
Features  
Ultra fast scan speed—1 kHz (nominal)  
Reliable finger detection through 5 mm thick acrylic  
Excellent EMI and AC noise immunity  
Low Power, Configurable CapSense™  
Configurable capacitive sensing elements  
2.4V to 5.25V operating voltage  
Low operating current  
• Active 1.5 mA (at 3.0V, 12 MHz)  
• Sleep 2.8 μA (at 3.3V)  
Supports up to 25 capacitive buttons  
Supports one slider  
Up to 10 cm proximity sensing  
Supports up to 28 General Purpose IO (GPIO) pins  
• Drive LEDs and other outputs  
Configurable LED behavior (fading, strobing)  
LED color mixing (RBG LEDs)  
Pull Up, High Z, Open Drain, and CMOS drive modes on all  
GPIO  
Internal ±5.0% 6 or12 MHz main oscillator  
Internal low speed oscillator at 32 kHz  
Low external component count  
• No external crystal or oscillator components  
• No external voltage regulator required  
Industry Best Flexibility  
8K Flash program storage 50,000 Erase and Write cycles  
512 bytes SRAM data storage  
Bootloader for ease of field reprogramming  
Partial Flash updates  
Flexible Flash protection modes  
Interrupt controller  
In-System Serial Programming (ISSP)  
Free complete development tool (PSoC Designer™)  
Full Featured, In-Circuit Emulator and Programmer  
• Full speed emulation  
• Complex breakpoint structure  
• 128K trace memory  
Additional System Resources  
Configurable communication speeds  
I2C Slave  
SPI Master and SPI Slave  
Watchdog and Sleep timers  
Internal voltage reference  
Integrated supervisory circuit  
Logic Block Diagram  
Port 3 Port 2 Port 1 Port 0  
3V LDO  
PSoC  
CORE  
System Bus  
Global Analog Interconnect  
SRAM  
512 Bytes  
SROM  
Flash 8K  
CPU Core  
(M8C)  
Sleep and  
Watchdog  
Interrupt  
Controller  
6/12 MHz Internal Main Oscillator  
Analog  
Ref.  
CapSense  
Basic  
Block  
ANALOG  
SYSTEM  
POR and LVD  
System Resets  
I2C Slave/SPI  
Master-Slave  
Analog  
Mux  
SYSTEM RESOURCES  
Cypress Semiconductor Corporation  
Document Number: 001-41947 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 15, 2009  
[+] Feedback  

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