Datasheet > CY8C20110

CY8C20110

更新时间： 2024-11-09 03:12:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	314K
描述
CapSenseLITE - 10 Configurable IOs

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CY8C20110 数据手册

CY8C20110

CapSenseLITE - 10 Configurable IOs

Features

Overview

■ Ten configurable IOs supporting

❐ CapSense buttons

❐ LED drive

❐ Interrupt outputs

❐ WAKE on interrupt input

❐ User defined input/output

The CapSenseLITE controller allows the control of ten IOs

configurable as capacitive sensing buttons or as GPIOs for

driving LEDs or interrupt signals based on various button

conditions. The GPIOs are also configurable for waking up the

device from sleep based on an interrupt input.

The user has the ability to configure buttons, outputs, and

parameters, through specific commands sent to the I²C port. The

IOs have the flexibility in mapping to capacitive buttons and as

standard GPIO functions such as interrupt output or input, LED

drive and digital mapping of input to output using simple logical

operations. This enables easy PCB trace routing and reduces

the PCB size and stack up. CapSenseLITE products are

designed for easy integration into complex products.

■ 2.4V to 5.25V operating voltage

■ Industrial temperature range: –40°C to +85°C

■ I²C slave interface for configuration

■ Reduce BOM cost

❐ Internal oscillator - no external oscillators or crystal

❐ Free development tool - no external tuning components

Architecture

■ Low operating current

❐ Active current: continuous sensor scan - 1mA

❐ Sleep current: no scan, continuous sleep - 2.6uA

The logic block diagram illustrates the internal architecture of

CY8C20110.

The user is able to configure registers with parameters needed

to adjust the operation and sensitivity of the CapSense system.

CY8C20110 supports a standard I²C serial communication

interface that allows the host to configure the device and to read

sensor information in real time through easy register access.

■ Available in 16-pin QFN and 16-pin SOIC packages

The CapSenseLITE Core

The CapSenseLITE Core has a powerful configuration and

control block. It encompasses SRAM for data storage, an

interrupt controller, along with sleep and watchdog timers.

System resources provide additional capability, such as a config-

urable I²C slave communication interface and various system

resets. The Analog system contains the CapSense PSoC block

and an internal 1.8V analog reference, which together support

capacitive sensing of up to 10 inputs.

Cypress Semiconductor Corporation

Document Number: 001-17345 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•408-943-2600

Revised November 22, 2007

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与CY8C20110相关器件

型号	品牌	获取价格	描述	数据表
CY8C20110_08	CYPRESS	获取价格	CapSense Express⑩-10 Configurable IOs
CY8C20110_0809	CYPRESS	获取价格	CapSense Express™-10 Configurable GPIOs with
CY8C20110_09	CYPRESS	获取价格	CapSense Express Button Capacitive Controllers
CY8C20110_12	CYPRESS	获取价格	CapSenseÂ® Expressâ¢ Button Capacitive Contr
CY8C20110_13	CYPRESS	获取价格	CapSenseÂ® Expressâ¢ Button Capacitive Contr
CY8C20110-LDX2I	CYPRESS	获取价格	CapSenseLITE - 10 Configurable IOs
CY8C20110-SX2I	CYPRESS	获取价格	CapSenseLITE - 10 Configurable IOs
CY8C20111	CYPRESS	获取价格	CapSense Express-One Button and Two Button Capacitive Controllers
CY8C20111_11	CYPRESS	获取价格	CapSense Express – One Button and Two Button
CY8C20111_12	CYPRESS	获取价格	CapSenseÂ® Expressâ¢ â One Button and Two

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